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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點DSP) |
| 中文描述： | 定點數(shù)字信號處理器（定點DSP）的 |
| 文件頁數(shù)： | 2/35頁 |
| 文件大小： | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
description (continued)
The TMS320UVC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UVC5409 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
For detailed information on the architecture of the ’C5000 family of DSPs, see the TMS320C5000 DSP Family
Functional Overview(literature number SPRU307).
C
H
A18
A17
VSS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
VSS
HPIENA
CVDD
VSS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
VSS
DVDD
BDX1
BFSX1
VSS
A22
VSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
VSS
VSS
CVDD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
VSS
BDR1
BFSR1
1
A
C
1
1
1
A
1
A
1
A
1
A
1
A
1
H
1
A
1
A
1
A
1
A
1
D
1
1
1
1
1
1
H
1
D
1
D
1
D
1
H
1
D
1
D
1
1
D
1
D
1
D
1
D
1
1
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
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6
1
2
3
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5
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13
14
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16
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18
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20
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22
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24
25
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28
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31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
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96
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93
92
91
90
89
88
87
86
85
84
83
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80
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78
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75
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73
B
H
S
V
B
B
B
B
B
H
B
B
B
S
V
D
D
S
V
H
B
B
I
H
N
I
I
I
I
D
C
H
S
V
H
H
1
S
1
A
1
7
7
7
B
D
A
D
D
C
H
S
V
D
D
D
D
PGE PACKAGE
(TOP VIEW)
B
A
B
S
V
S
V
S
V
NC = No internal connection
DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O
pins and the core CPU.
A
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