
TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMA controller
The ’UVC5409 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA controller allows movements of data to and from internal
program/data memory, internal peripherals (such as the McBSPs), and external program/data memory to occur
in the background of CPU operation. The DMA has six independent programmable channels allowing six
different contexts for DMA operation.
features
The DMA has the following features:
The DMA has external memory access.
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
Each read or write transfer may be initialized by selected events. (Internally only)
Each DMA channel is capable of sending interrupts to the CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)
DMA external access
The ’UVC5409 DMA supports external accesses to extended program and extended data memory.
Only two channels are available for external accesses. (One for external reads/one for external writes.)
Single-word transfers are supported for external accesses.
The DMA does not support transfers from peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
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