參數(shù)資料
型號(hào): TMS320VC5409GGU100
廠商: Texas Instruments
文件頁(yè)數(shù): 40/93頁(yè)
文件大?。?/td> 0K
描述: IC DIG SIG PROCESSOR 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時(shí)鐘速率: 100MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤(pán)
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
其它名稱: 296-10763
296-10763-5
296-10763-5-ND
Functional Overview
45
April 1999 Revised October 2008
SPRS082F
3.3.6 Peripheral Memory-Mapped Registers
The device provides a set of memory-mapped registers associated with peripherals. Table 34 gives a list of
CPU memory-mapped registers (MMRs) available on 5409. Table 316 shows additional peripheral MMRs
associated with the 5409.
Table 316. Peripheral Memory-Mapped Registers
NAME
ADDRESS
DESCRIPTION
TYPE
DRR20
20h
Data receive register 2
McBSP #0
DRR10
21h
Data receive register 1
McBSP #0
DXR20
22h
Data transmit register 2
McBSP #0
DXR10
23h
Data transmit register 1
McBSP #0
TIM
24h
Timer register
Timer
PRD
25h
Timer period counter
Timer
TCR
26h
Timer control register
Timer
27h
Reserved
SWWSR
28h
Software wait-state register
External Bus
BSCR
29h
Bank-switching control register
External Bus
2Ah
Reserved
SWCR
2Bh
Software wait-state control register
External Bus
HPIC
2Ch
HPI control register
HPI
2Dh2Fh
Reserved
DRR22
30h
Data receive register 2
McBSP #2
DRR12
31h
Data receive register 1
McBSP #2
DXR22
32h
Data transmit register 2
McBSP #2
DXR12
33h
Data transmit register 2
McBSP #2
SPSA2
34h
McBSP2 subbank address register
McBSP #2
SPSD2
35h
McBSP2 subbank data register
McBSP #2
3637h
Reserved
SPSA0
38h
McBSP0 subbank address register
McBSP #0
SPCD0
39h
McBSP0 subbank data register
McBSP #0
3Ah3Bh
Reserved
GPIOCR
3C
General-purpose I/O pins control register
GPIO
GPIOSR
3D
General-purpose I/O pins status register
GPIO
3E3F
Reserved
DRR21
40h
Data receive register 1
McBSP #1
DRR11
41h
Data receive register 2
McBSP #1
DXR21
42h
Data transmit register 1
McBSP #1
DXR11
43h
Data transmit register 2
McBSP #1
44h47h
Reserved
SPSA1
48h
McBSP1 subbank address register
McBSP #1
SPCD1
49h
McBSP1 subbank data register
McBSP #1
4Ah53h
Reserved
DMPREC
54h
DMA channel priority and enable control register
DMA
DMSA
55h
DMA subbank address register
DMA
DMSDI
56h
DMA subbank data register with autoincrement
DMA
DMSDN
57h
DMA subbank data registrer
DMA
CLKMD
58h
Clock mode register
PLL
59h5Fh
Reserved
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