參數(shù)資料
型號: TMS320VC5409ZGU100
廠商: Texas Instruments
文件頁數(shù): 16/93頁
文件大?。?/td> 0K
描述: IC FIXED POINT DSP 144-BGA
標準包裝: 160
系列: TMS320C54x
類型: 定點
接口: 主機接口,McBSP
時鐘速率: 100MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
23
April 1999 Revised October 2008
SPRS082F
15
8
Reserved
R/W-0
7
10
Reserved
SWSM
R/W-0
R/W0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 33. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]
Table 32. Software Wait-State Configuration Register (SWCR) Bit Fields
PIN
RESET
FUNCTION
NO.
NAME
RESET
VALUE
FUNCTION
151
Reserved
0
These bits are reserved and are unaffected by writes.
0
SWSM
0
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.1.2 Programmable Bank-Switching Wait States
The programmable bank-switching logic of the 5409 is functionally equivalent to that of the 548/549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program
or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross
the data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 34
shows the BSCR and its bits are described in Table 33.
15
12
11
10
8
BNKCMP
PSDS
Reserved
R/W-1111
R/W1
R0
7
32
1
0
Reserved
HBH
BH
EXIO
R0
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
Figure 34. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
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