參數(shù)資料
型號: TMS320VC5409ZGU100
廠商: Texas Instruments
文件頁數(shù): 26/93頁
文件大小: 0K
描述: IC FIXED POINT DSP 144-BGA
標(biāo)準(zhǔn)包裝: 160
系列: TMS320C54x
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP
時鐘速率: 100MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 64kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.80V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA
供應(yīng)商設(shè)備封裝: 144-BGA MICROSTAR(12x12)
包裝: 托盤
配用: 296-15829-ND - DSP STARTER KIT FOR TMS320C5416
Functional Overview
32
April 1999 Revised October 2008
SPRS082F
3.3.2 Multichannel Buffered Serial Ports (McBSPs)
The 5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other 54x devices. Like its predecessors, the McBSP provides:
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
Direct interface to:
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
Serial peripheral interface (SPI) devices
Multichannel transmit and receive of up to 32 channels in a 128 channel stream.
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
For detailed information on the standard features of the McBSP, refer to the TMS320C54x DSP Reference
Set, Volume 5: Enhanced Peripherals, (literature number SPRU302).
Although the BCLKS pin is not available on the 5409 PGE and GGU packages, the 5409 is capable of
synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for
external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
15
14
13
12
11
10
9
8
Reserved
XIOEN
RIOEN
FSXM
FSRM
CLKXM
CLKRM
RW
7654
3210
SCLKME
CLKS STAT
DX STAT
DR STAT
FSXP
FSRP
CLKXP
CLKRP
RW
LEGEND: R = Read, W = Write
Figure 38. Pin Control Register (PCR)
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