- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄19456 > TMS320VC5409ZGU100 (Texas Instruments)IC FIXED POINT DSP 144-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | TMS320VC5409ZGU100 |
| 廠(chǎng)商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 21/93頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FIXED POINT DSP 144-BGA |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | TMS320C54x |
| 類(lèi)型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，McBSP |
| 時(shí)鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（32 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 144-BGA MICROSTAR（12x12） |
| 包裝： | 托盤(pán) |
| 配用： | 296-15829-ND - DSP STARTER KIT FOR TMS320C5416 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Functional Overview
28
April 1999 Revised October 2008
SPRS082F
3.2.5 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE:The hardware reset (RS) vector cannot be remapped because a hardware reset loads
the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program
space.
3.2.6 Extended Program Memory
The 5409 CPU uses a paged extended memory scheme in program space to allow access of up to 8M program
memory locations. In order to implement this scheme, the 5409 includes several features that are also present
on the 548/549 devices:
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC register defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
Six extra instructions for addressing extended program space. These six instructions affect the XPC.
FB[D] pmad (23 bits) Far branch
FBACC[D] Accu[22:0] Far branch to the location specified by the value in accumulator A or
accumulator B
FCALL[D] pmad (23 bits) Far call
FCALA[D] Accu[22:0] Far call to the location specified by the value in accumulator A or
accumulator B
FRET[D] Far return
FRETE[D] Far return with interrupts enabled
In addition to these new instructions, two 54x instructions are extended to use 23 bits in the 5409:
READA data_memory (using 23-bit accumulator address)
WRITA data_memory (using 23-bit accumulator address)
All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the 5409 is organized into 127 pages that are each 64K in length, as shown in Figure 36.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T491D107K010AH | CAP TANT 100UF 10V 10% 2917 |
| ASC36DREN-S13 | CONN EDGECARD 72POS .100 EXTEND |
| TWR-5/3000-15/500-D12A-C | CONV DC/DC TRI OUT 5,15,-15V |
| EEM22DRYN-S13 | CONN EDGECARD 44POS .156 EXTEND |
| ASC36DREH-S13 | CONN EDGECARD 72POS .100 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320VC5409ZGU-80 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5410AGGU1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMS320VC5410AGGU12 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5410AGGU16 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320VC5410APGE12 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。