參數(shù)資料
型號: TMS470R1A384PZQ
廠商: Texas Instruments
文件頁數(shù): 39/62頁
文件大?。?/td> 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標準包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 384KB(384K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 管件
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
SPIn SLAVE MODE TIMING PARAMETERS
SPIn Slave Mode External Timing Parameters
SPInSIMO
SPInSOMI
SPInCLK
(clock polarity = 1)
SPInCLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
1
2
3
4
5
6
5
7
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1) (2) (3) (4) (see Figure 15)
NO.
MIN
MAX
UNIT
1
tc(SPC)S
Cycle time, SPInCLK(5)
100
256tc(ICLK)
ns
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
2(6)
ns
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
3(6)
ns
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
Delay time, SPInCLK high to SPInSOMI valid
td(SPCH-SOMI)S
6 + tr
(clock polarity = 0)
4(6)
ns
Delay time, SPInCLK low to SPInSOMI valid
td(SPCL-SOMI)S
6 + tf
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
tv(SPCH-SOMI)S
tc(SPC)S - 6 - tr
(clock polarity = 0)
5(6)
ns
Valid time, SPInSOMI data valid after SPInCLK low
tv(SPCL-SOMI)S
tc(SPC)S - 6 - tf
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK low
tsu(SIMO-SPCL)S
6
(clock polarity = 0)
6(6)
ns
Setup time, SPInSIMO before SPInCLK high
tsu(SIMO-SPCH)S
6
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK low
tv(SPCL-SIMO)S
6
(clock polarity = 0)
7(6)
ns
Valid time, SPInSIMO data valid after SPInCLK high
tv(SPCH-SIMO)S
6
(clock polarity = 1)
(1)
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
(2)
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(5)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
(6)
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
44
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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