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參數(shù)資料
型號(hào): TMS470R1A384PZQ
廠商: Texas Instruments
文件頁(yè)數(shù): 32/62頁(yè)
文件大小: 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
標(biāo)準(zhǔn)包裝: 90
系列: TMS470
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 48MHz
連通性: CAN,C2Slb,I²C,SCI,SPI
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 384KB(384K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 2.05 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 100-LQFP
包裝: 管件
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
RST AND PORRST TIMINGS
Timing Requirements for PORRST
VCCP /VCCIO
VCC
VCCPORH
VCCIOPORL
VIL(PORRST)
VCCIOPORH
VCCIOPORL
VCCPORL
VCC
PORRST
VCCIO
VCCPORH
VCCPORL
VIL
VIL(PORRST)
VCCP/VCCIO
VCC
th(PORRST)rio
th(PORRST)r
tsu(PORRST)f
th(PORRST)r
tsu(PORRST)fio
tsu(PORRST)f
tsu(VCCIO)f
tsu(VCCIO)r
tsu(PORRST)r
th(PORRST)d
Switching Characteristics Over Recommended Operating Conditions for RST
(1)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
(see Figure 9)
MIN
MAX UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
0.6
V
VCC high supply level when PORRST must remain active during power up and become
VCCPORH
1.5
V
active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
1.1
V
VCCIO high supply level when PORRST must remain active during power up and become
VCCIOPORH
2.75
V
active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
0.2 VCCIO
V
VIL(PORRST)
Low-level input voltage of PORRST before V CCIO > VCCIOPORL
0.5
V
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
s
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
NOTE: VCCIO > 1.1 V before VCC > 0.6 V
Figure 9. PORRST Timing Diagram
PARAMETER
MIN
MAX UNIT
Valid time, RST active after PORRST inactive
4112tc(OSC)
tv(RST)
ns
Valid time, RST active (all others)
8tc(SYS)
Flash start-up time, from RST inactive to fetch of first instruction from flash (flash pump
tfsu
360tc(OSC)
ns
stabilization time)
(1)
Specified values do NOT include rise/fall times. For rise and fall timings, see the "Switching Characteristics for Output Timings versus
Load Capacitance" table.
38
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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