參數(shù)資料
型號(hào): TMX320F2810GHHMEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 33/103頁(yè)
文件大小: 1341K
代理商: TMX320F2810GHHMEP
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
APRIL 2001
REVISED SEPTEMBER 2001
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
XINTCNF2 register (continued)
Table 15. XINTCNF2 Register Bit Definitions (Continued)
BITS
TYPE
NAME
RESET
DESCRIPTION
15:12
X
Reserved
0
Reserved
18:16
R/W
XTIMCLK
0,0,1
These bits select the fundamental clock for the timing of lead, active and trail
switching operations as defined by the XTIMING and XBANK registers:
Mode
Action
0,0,0
0,0,1
0,1,0
0,1,1
1,0,0
1,0,1
1,1,0
1,1,1
XTIMCLK = SYSCLKOUT/1
XTIMCLK = SYSCLKOUT/2
reserved
reserved
reserved
reserved
reserved
reserved
XBANK register
Table 16. XBANK Register Bit Defintions
BITS
TYPE
NAME
RESET
DESCRIPTION
2:0
R/W
BANK
1,1,1
These bits specify the XINTF zone for which bank switching is enabled, ZONE
0 to ZONE 7. At reset, XINTF Zone 7 is selected.
5:3
R/W
BCYC
1,1,1
These bits specify the number of XTIMCLK cycles to add between any
consecutive access that crosses into or out of the specified zone, be it a read or
write, program or data space. The number of XTIMCLK cycles can be 0 to 14.
On a reset (XRS) the value defaults to 14 cycles.
14:6
X
Reserved
15
R/W
Reserved
1
XREVISION register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the F2812, this register will be configured as described in Table 17.
Table 17. XREVISION Register Bit Defintions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
15
0
REVISION
R
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
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