參數(shù)資料
型號: TMX320F2810GHHMEP
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 91/103頁
文件大小: 1341K
代理商: TMX320F2810GHHMEP
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
APRIL 2001
REVISED SEPTEMBER 2001
91
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
GPIO mux (continued)
Table 66. GPDMUX, GPDDIR Register Bit Definitions
GPDMUX
BIT
PERIPHERAL NAME (BIT = 1)
GPIO NAME
(BIT = 0)
GPDDIR BIT
TYPE
RESET
INPUT QUAL
EV-A Peripheral:
0
T1CTRIP_PDPINTA (I)
GPIOD0
0
R/W
0
yes
1
T2CTRIP (I)
GPIOD1
1
R/W
0
yes
2
reserved
GPIOD2
2
R/W
0
3
reserved
GPIOD3
3
R/W
0
4
reserved
GPIOD4
4
R/W
0
EV-B Peripheral:
5
T3CTRIP_PDPINTB (I)
GPIOD5
5
R/W
0
yes
6
T4CTRIP (I)
GPIOD6
6
R/W
0
yes
7
reserved
GPIOD7
7
R=0
0
8
reserved
GPIOD8
8
R=0
0
9
reserved
GPIOD9
9
R=0
0
10
reserved
GPIOD10
10
R/W
0
11
reserved
GPIOD11
11
R/W
0
12
reserved
GPIOD12
12
R=0
0
13
reserved
GPIOD13
13
R=0
0
14
reserved
GPIOD14
14
R=0
0
15
reserved
GPIOD15
15
R=0
0
Table 67. GPDQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
7:0
QUALPRD
R/W
0:0
Specifies the qualification sampling period:
0x00
no qualification (just SYNC to SYSCLKOUT)
0x01
QUALPRD = SYSCLKOUT/2
0x02
QUALPRD = SYSCLKOUT/4
.
0xFF
QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
P
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