參數(shù)資料
型號(hào)： TMX320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 21/103頁(yè)
文件大小： 1341K
代理商： TMX320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
serial port peripherals
The F2810 and F2812 support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of the
SPI. On the F2810 and the F2812, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F2810 and the F2812, the port supports a 16-level, receive and
transmit FIFO for reducing servicing overhead.
McBSP:
SPI:
SCI:
register map
The F2810 device contains three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 4.
Peripheral Frame 1:
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 5.
Peripheral Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 6.
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