參數(shù)資料
型號： TMX320F2810PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 77/103頁
文件大?。?/td> 1341K
代理商： TMX320F2810PBKS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
77
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
multichannel buffered serial port (McBSP) module (continued)
Table 56 provides a summary of the McBSP registers.
Table 56. McBSP Register Summary
NAME
ADDRESS
0x000 xxh
TYPE
(R/W)
DATA REGISTERS, RECEIVE, TRANSMIT
RESET VALUE
(HEX)
DESCRIPTION
–
–
–
0x0000
McBSP Receive Buffer Register
–
–
–
0x0000
McBSP Receive Shift Register
–
–
–
0x0000
McBSP Transmit Shift Register
DRR2
00
R
0x0000
McBSP Data Receive Register 2
–
Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR1
01
R
0x0000
McBSP Data Receive Register 1
–
Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
W
0x0000
McBSP Data Transmit Register 2
–
Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
W
0x0000
McBSP Data Transmit Register 1
–
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
04
R/W
0x0000
McBSP Serial Port Control Register 2
SPCR1
05
R/W
0x0000
McBSP Serial Port Control Register 1
RCR2
06
R/W
0x0000
McBSP Receive Control Register 2
RCR1
07
R/W
0x0000
McBSP Receive Control Register 1
XCR2
08
R/W
0x0000
McBSP Transmit Control Register 2
XCR1
09
R/W
0x0000
McBSP Transmit Control Register 1
SRGR2
0A
R/W
0x0000
McBSP Sample Rate Generator Register 2
SRGR1
0B
R/W
0x0000
McBSP Sample Rate Generator Register 1
MULTICHANNEL CONTROL REGISTERS
MCR2
0C
R/W
0x0000
McBSP Multichannel Register 2
MCR1
0D
R/W
0x0000
McBSP Multichannel Register 1
RCERA
0E
R/W
0x0000
McBSP Receive Channel Enable Register Partition A
RCERB
0F
R/W
0x0000
McBSP Receive Channel Enable Register Partition B
XCERA
10
R/W
0x0000
McBSP Transmit Channel Enable Register Partition A
XCERB
11
R/W
0x0000
McBSP Transmit Channel Enable Register Partition B
PCR1
12
R/W
0x0000
McBSP Pin Control Register
RCERC
13
R/W
0x0000
McBSP Receive Channel Enable Register Partition C
RCERD
14
R/W
0x0000
McBSP Receive Channel Enable Register Partition D
XCERC
15
R/W
0x0000
McBSP Transmit Channel Enable Register Partition C
XCERD
16
R/W
0x0000
McBSP Transmit Channel Enable Register Partition D
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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