參數(shù)資料
型號： TMX320F2810PGFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 28/103頁
文件大?。?/td> 1341K
代理商： TMX320F2810PGFA
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
external interface, XINTF (F2812 only) (continued)
The operation and timing of the external interface, can be controlled by the registers listed in Table 13.
Table 13. XINTF Configuration and Control Register Mappings
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XTIMING0
0x0000
–
0B20
2
XINTF Timing Register, Zone 0
XTIMING1
0x0000
–
0B22
2
XINTF Timing Register, Zone 1
XTIMING2
0x0000
–
0B24
2
XINTF Timing Register, Zone 2
XTIMING6
0x0000
–
0B2C
2
XINTF Timing Register, Zone 6
XTIMING7
0x0000
–
0B2E
2
XINTF Timing Register, Zone 7
XINTCNF2
0x0000
–
0B34
2
XINTF Configuration Register
XBANK
0x0000
–
0B38
1
XINTF Bank Control Register
XREVISION
0x0000
–
0B3A
1
XINTF Revision Register
timing registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect to
XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 4.
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
1
0
XCLKOUT
/2
XTIMCLK
1
0
/2
C28x
CPU
XINTCNF2 (CLKMODE)
XINTCNF2 (XTIMCLK)
Default Value after reset
SYSCLKOUT
Figure 4. Relationship Between XTIMCLK and SYSCLKOUT
P
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