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參數(shù)資料
| 型號： | TMX320F2810PGFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 31/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320F2810PGFA |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
XINTCNF2 register
Table 15. XINTCNF2 Register Bit Definitions
BITS
TYPE
NAME
RESET
DESCRIPTION
1,0
R/W
Write
Buffer
Depth
0,0
The write buffer allows the processor to continue execution without waiting for
XINTF write accesses to complete. The write buffer depth is selectable as follows:
Depth
Action
00
No write buffering. The CPU will be stalled until the write
completes on the XINTF.
Note:
Default mode on reset (XRS).
01
The XINTF will buffer one word. The CPU is stalled until the
write cycle begins on the XINTF (there could be a read cycle
currently active on the XINTF).
10
One write will be buffered without stalling the CPU. The CPU
is stalled if a second write follows. The CPU will be stalled
until the first write begins its cycle on the XINTF.
11
Two writes will be buffered without stalling the CPU. The CPU
is stalled if a third write follows. The CPU will be stalled until
the first write begins its cycle on the XINTF.
The buffered access can be 8, 16, or 32 bits in length. Order of execution is
preserved, e.g., writes are performed in the order they were accepted. The
processor is stalled on XINTF reads until all pending writes are done and the read
access completes. If the buffer is full, any pending reads or writes to the buffer
will stall the processor.
The
“
Write Buffer Depth
”
can be changed; however, it is recommended that the
write buffer depth be changed only when the buffer is empty (this can be checked
by reading the
“
Write Buffer Level
”
bits). Writing to these bits when the level is not
zero may have unpredictable results.
2
R/W
CLKMODE
Mode
1
XCLKOUT divide by 2 mode. If this bit is set to 1, XCLKOUT is a divide by 2 of
XTIMCLK. If this bit is set to 0, XCLKOUT is equal to XTIMCLK. All bus timings,
irrespective of which mode is enabled, will start from the rising edge of XCLKOUT.
The default mode of operation on power up and reset is /2 mode.
3
R/W
CLKOFF
0
Turn XCLKOUT off mode. When this bit is set to 1, the XCLKOUT signal is turned
off. This is done for power savings and noise reduction. This bit is set to 0 on a
reset.
4
R
Reserved
1
Reserved
5
R
Reserved
0
Reserved
P
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| TMP320F2810PGFA | DIGITAL SIGNAL PROCESSORS |
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| TMP320F2810PGFAEP | Digital Signal Processors |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TMX320F2810PGFAEP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
| TMX320F2810PGFS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
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| TMX320F2811GHHQ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMX320F2811GHHS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
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