參數(shù)資料
型號： TMX320F2810PGFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 40/103頁
文件大?。?/td> 1341K
代理商： TMX320F2810PGFA
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PIE registers (continued)
Table 23. PIECTRL Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
ENPIE
R/W
0
Enable vector fetching from PIE block. When this bit is set to 1, all vectors are fetched from
the PIE vector table. If this bit is set to 0, the PIE block is disabled and vectors are fetched
as normal. All PIE block registers (PIEACK, PIEIFR, PIEIER) can be accessed even when
the PIE block is disabled.
15:1
PIEVECT
R
0
Vector fetch address. Displays the address of the vector that was fetched. The least
significant bit of the address is ignored and only bits 1 to 15 are shown. The vector address
can be used to determine which interrupt generated the fetch.
Table 24. PIEACK Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
11:0
PIEACK
R/W=1
0
Writing a 1 to the respective interrupt bit enables the PIE block to drive a pulse into the CPU
interrupts input, if an interrupt is pending on any of the group interrupts. Reading this
register indicates if an interrupt is pending in the respective group. Bit 0 refers to INT1 up
to Bit 11, which refers to INT12.
Note:
Writes of 0 are ignored.
15:12
spares
R=0
0
Table 25. PIEIERx Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
1
INTx.1
INTx.2
R/W
R/W
0
0
2
INTx.3
R/W
0
3
INTx.4
R/W
0
Theseregister bits individually enable an interrupt within a group They behave very much
These register bits individually enable an interrupt within a group. They behave very much
like the CPU interrupt enable register. Setting a bit to 1 will enable the servicing of the
like the CPU interru t enable register. Setting a bit to 1 will enable the servicing of the
respective interrupt. Setting a bit to 0 will disable the servicing of the bit.
4
INTx.5
R/W
0
5
INTx.6
R/W
0
6
INTx.7
R/W
0
7
INTx.8
R/W
0
15:8
spares
R=0
0
x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
Table 26. PIEIFRx Register Bit Definitions
BIT(S)
0
1
NAME
INTx.1
INTx.2
TYPE
R/W
R/W
RESET
0
0
DESCRIPTION
2
INTx.3
R/W
0
These register bits indicate if an interrupt is currently active. They behave very much like
th CPUi t
tfl
i t
i t
the CPU interrupt flag register. When an interrupt is active, the respective register bit is set.
The bit is cleared when the interrupt is serviced or by writing a 0 to the register bit This
The bit is cleared when the interrupt is serviced or by writing a 0 to the register bit. This
register can also be read to determine which interrupts are active or pending.
register can also be read to determine which interru ts are active or ending.
i t
biti
3
INTx.4
R/W
0
4
INTx.5
R/W
0
5
INTx.6
R/W
0
Note:
The PIEIFR register bit is cleared during the interrupt vector fetch portion of
the interrupt processing.
6
INTx.7
R/W
0
7
INTx.8
R/W
0
15:8
spares
R=0
0
x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
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