參數(shù)資料
型號(hào)： TNETA1555
廠商： Texas Instruments, Inc.
英文描述： 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時(shí)鐘恢復(fù)裝置)
中文描述： 155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置（155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置）
文件頁數(shù)： 1/10頁
文件大?。?/td> 230K
代理商： TNETA1555
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V
CC
CPLL
GND
DIN
INDIS
DIN
V
CC
GND
TESTOUT
GND
V
CC
DATAOUT
TEST1
TEST2
V
CC
CLK
CLK
GND
DOUT
DOUT
V
CC
DATAIN
DATAIN
DATAOUT
DW PACKAGE
(TOP VIEW)
TNETA1555
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS001B – SEPTEMBER 1992 – REVISED DECEMBER 1994
Copyright
1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Recovers a 155.52-MHz Clock Signal From
a 155.52-Mbit/s STS-3/STM-1 NRZ Data
Stream
Accepts Pseudo-ECL (PECL) Input Voltage
Levels on the Input Data Stream
Provides a Separate Pseudo-ECL-to-True-
ECL Converter for an Additional Data
Signal Requiring Conversion
Requires a Single 5-V Supply
description
The TNETA1555 device recovers an embedded
clock signal from a 155.52-Mbit/s STS-3/STM-1
nonreturn-to-zero (NRZ) data stream using a
frequency/phase-locked loop. The device accepts
PECL (ECL signals referenced to 5 V instead of GND) input-voltage levels. The recovered clock and data
outputs are PECL compatible. The serial data input and recovered clock and data outputs are differential to
provide maximum noise immunity.
The input disable (INDIS) disconnects the incoming serial data stream from the clock-recovery circuitry. When
the INDIS input is high, the data output is forced low and the clock-recovery circuitry maintains the output
frequency present at the time the input was disabled for a specific amount of time. This time is dependent upon
the value of the capacitor in the loop filter.
A PECL-to-ECL converter is included in the device for those applications where an interface between the two
different voltage levels is required. An example of such an application is an optical transmitter that requires ECL
input voltage levels and a parallel-to-serial converter with pseudo-ECL-level outputs.
The TNETA1555 requires only a positive 5-V supply (5 V
±
5 %) for operation. The device is characterized for
operation over a temperature range of –40
°
C to 85
°
C.
functional block diagram
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INDIS
DIN
DIN
Clock Recovery
(frequency/
phase-locked loop)
17
18
21
20
DOUT
DOUT
CLK
CLK
PECL-to-ECL
Converter
14
15
13
12
DATAIN
DATAIN
DATAOUT
DATAOUT
2
CPLL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
相關(guān)PDF資料
PDF描述
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TNETA1600 SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
TNETA1610 STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器)
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