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參數(shù)資料
| 型號： | TNETA1561 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ATM Segmentation and Reassembly Device with PCI Host Interface(ATM 分段和重設裝置帶SBUS主機接口) |
| 中文描述： | 自動柜員機分段和重組的PCI主機接口（自動柜員機分段和重設裝置帶SBU的主機接口設備） |
| 文件頁數(shù)： | 1/49頁 |
| 文件大?。?/td> | 976K |
| 代理商： | TNETA1561 |
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TNETA1561
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI HOST INTERFACE
SDNS028B – OCTOBER 1994 – REVISED JANUARY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Peripheral Component Interconnect (PCI)
Device That Provides Asynchronous
Transfer-Mode (ATM) Interface
Single-Chip Segmentation and
Reassembly (SAR) for Full-Duplex ATM
Adaptation-Layer (AAL) Processing
On-Chip PCI Host Interface Allows Use of
Host Memory for Packet SAR
53-Byte ATM Cells Are Transparent to the
User
Provides Complete Encapsulation and
Termination of AAL5 and Limited AAL3/4
Features a Null AAL That Provides
Functions for Constant-Bit-Rate Services
Supports 1023 Unique Virtual Circuits
(VCs) on Receive Side
Explicit Cell-Level Interleaving Between
Groups of VCs
Packet Interface Is Managed by Efficient
Descriptor Rings
Physical (PHY)-Layer Interface Is Full
Duplex and Compliant to the ATM Forum
UTOPIA Contribution
Supports PHY-Layer Data Rates in the
Range of 25.6 Mbit/s to 155.52 Mbit/s
Interfaces Directly to the TNETA1500
SONET ATM BiCMOS Receiver/Transmitter
(SABRE)
Recognizes ATM-Layer Operation and
Maintenance (OAM) Cells
No External Logic Required for Host or
Local Buses to Ensure Simple Design
Supports an External EPROM for System
Configuration Code
description
The TNETA1561 (PCI SAR) is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR)
device with a peripheral component interconnect (PCI)-bus interface. This device incorporates ATM
adaptation-layer (AAL) processing, ATM SAR processing for full-duplex operation up to STS-3c rate of
155.52 Mbit/s, and the controls for the register interface on the physical (PHY) layer. The TNETA1561 provides
a packet interface that is managed by descriptor rings, making the 53-byte ATM-framing format transparent to
the user. The device passes the payload of 48 bytes, constituting the payload of each cell, across the PCI-host
interface. All packets are segmented and reassembled in host memory and accessed by the chip via the
descriptor-ring mechanism. The device reduces the memory requirements for network-interface cards (NICs).
The TNETA1561 requires no local processor on the card, which enables very compact solutions.
The applications for the TNETA1561 include NICs for client workstations and servers, embedded applications
like LAN emulation, and multiprotocol systems like video servers. The TNETA1561 provides complete AAL5
encapsulation and termination in hardware. In addition, limited support is provided for AAL 3/4 and a null AAL
is provided to facilitate real-time data transfer. The TNETA1561 recognizes ATM-layer operation and
maintenance (OAM) cells.
In the transmit direction, the TNETA1561 generates data via a special bit-rate control table that provides explicit
cell-level interleaving between groups of virtual circuits (VCs). This mechanism brings a higher degree of
flexibility when specifying peak rates for each group (up to 155.52 Mbit/s at a resolution greater than 32 kbit/s).
The VCs within a group are serviced via a first-in, first-out (FIFO) discipline on a per-packet basis.
In the receive direction, the TNETA1561 allows multiple virtual paths (VPs) with the condition that each VC is
unique. The device is primarily intended for AAL5 encapsulation and termination that is supported in hardware.
The TNETA1561 has four interfaces that include the following: the PCI-bus interface with a 32-bit-wide data bus,
the cell interface based on the universal test and operations interface for ATM (UTOPIA specification), a
control-memory interface to access the local SRAM, and the local-bus interface to access the PHY-layer
registers. The UTOPIA interface to the PHY layer consists of an 8-bit-wide datapath and associated control
signals in both the transmit and receive directions. The 53-byte ATM cells pass between the ATM and PHY
layers through the UTOPIA interface.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關PDF資料 |
PDF描述 |
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| TNETA1600 | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
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| TO-252 | TO-252 (MP-3Z) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1561PGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1570 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE |
| TNETA1570MFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| TNETA1570PGW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TNETA1575 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES |
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