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參數(shù)資料
| 型號： | TNETA1555 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時鐘恢復(fù)裝置) |
| 中文描述： | 155.52 - Mbit / s的時鐘恢復(fù)裝置（155.52 - Mbit / s的時鐘恢復(fù)裝置） |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 230K |
| 代理商： | TNETA1555 |
TNETA1555
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS001B – SEPTEMBER 1992 – REVISED DECEMBER 1994
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
transitionless bit periods (continued)
800
400
200
0
– 40
600
– 20
TA – Operating Free-Air Temperature –
°
C
0
20
40
N
1000
MAXIMUM NUMBER OF HIGH BITS
WITHOUT A BIT ERROR
60
80
100
400
200
100
0
– 40
300
– 20
TA – Operating Free-Air Temperature –
°
C
0
20
40
N
MAXIMUM NUMBER OF LOW BITS
WITHOUT A BIT ERROR
60
80
100
900
700
600
500
800
1000
VCC = 4.75 V
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
VCC = 5.25 V
VCC = 5 V
Figure 3
Figure 4
jitter transfer (peaking and bandwidth)
SONET/SDH regenerator interfaces are required to meet jitter-transfer requirements. Jitter transfer is the ratio
of measured output jitter to applied input jitter, and it is measured in decibels. Meeting the jitter-transfer
requirement in SONET/SDH regenerators requires either a clock-recovery circuit with a voltage-controlled
crystal oscillator (VCXO) or a similar technique that provides extremely low jitter. The TNETA1555 provides a
typical jitter-transfer bandwidth of approximately 2 MHz. This is where the device begins to attenuate the input
jitter so that the output jitter is less than the input jitter. The device exhibits minimal jitter peaking when a capacitor
of approximately 0.1
μ
F is used in the loop filter. The peaking is less than 0.3 dB, which is the resolution of the
test equipment used to measure this parameter.
external connections
loop-filter capacitor
The capacitor for the loop filter is connected from terminal 2 of the TNETA1555 to ground. It is recommended
that a 0.1-
μ
F chip capacitor be used. A smaller capacitor reduces the amount of acquisition time required for
the device to lock on to the input data stream while it increases the amount of jitter peaking that can occur. A
larger capacitor results in a longer acquisition time and does not provide any noticeable increase in jitter
performance.
signal connections
Figure 5 shows a typical connection between the TNETA1555, an optical-to-electrical converter, and a framer
device. The TNETA1555 accepts pseudo-ECL compatible signals at the serial data inputs DIN and DIN. The
retimed pseudo-ECL clock outputs are provided at outputs CLK and CLK. The pseudo-ECL inputs and outputs
require a 50-
termination to V
CC
–2 V (or a Thevenin equivalent). The Thevenin equivalent circuit consists of
an 82-
resistor to V
CC
and 120-
resistor to ground.
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