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參數(shù)資料
| 型號(hào)： | TNETA1555 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時(shí)鐘恢復(fù)裝置) |
| 中文描述： | 155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置（155.52 - Mbit / s的時(shí)鐘恢復(fù)裝置） |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 230K |
| 代理商： | TNETA1555 |
TNETA1555
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS001B – SEPTEMBER 1992 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
introduction
The TNETA1555 provides clock recovery and data retiming on a nonreturn to zero (NRZ) serial-input data
stream. The device uses an analog phase-locked loop (APLL) with an integrated voltage controlled oscillator
(VCO) to recover the imbedded clock signal from incoming data. A loop-filter capacitor is the only external
component required for the proper operation of the device. The TNETA1555 is designed for operation with a
155.52-Mbit/s serial-input data stream. The device has pseudo-ECL compatible inputs and outputs and
operates from a single 5-V supply. Pseudo-ECL levels are referenced to 5 V instead of ground.
Since the incoming 155.52-Mbit/s serial-input data stream does not contain a 155.52-MHz frequency
component, a transition detector, shown on the clock-recovery block diagram, is used as a frequency doubler
to generate this frequency. The output of the transition detector is passed to a phase/frequency detector where
it is compared to the output of the VCO. The phase/frequency detector is actually comprised of two circuits. One
circuit provides a coarse frequency-detection capability and a second provides a finer phase adjustment. The
phase/frequency detector compares the signal from the transition detector to the VCO output and generates
signals to either increase or decrease the VCO frequency, depending upon whether the VCO frequency is less
than or greater than the frequency of the signal from the transition detector. The up/down pulses are sent to the
charge pump/loop filter for conversion to a bias voltage that sets the VCO output frequency.
The process of comparing the input signal frequency and the VCO output frequency is continuous and
eventually results in the VCO output frequency equaling the frequency of the input signal. The device also allows
the VCO output to react to changes in the input signal due to jitter. The recovered clock output is sent from the
VCO to the retiming circuit where the input data is retimed to the recovered clock. The retiming circuit centers
the output clock in the middle of the output data.
clock-recovery block diagram
DOUT
DOUT
CLK
CLK
Retiming
Circuit
Transition
Detector
Phase/Frequency
Detector
Charge Pump/
Loop Filter
Voltage-
Controlled
Oscillator
Recovered
Clock
DIN
CPLL
performance measurements
Measuring the performance of a clock-recovery circuit involves determining how well the circuit operates in the
presence of jitter. Jitter is defined as the short-term variations of digital signals significant instants from their ideal
positions in time.
For testing purposes, jitter is usually generated by modulating a digital data sequence with
a sinusoidal waveform of a known frequency. This results in a digital data stream where the widths of the
individual data pulses vary with time. The amount of pulse-width variation can be changed by altering the
frequency and amplitude of the modulating signal, which changes the amount of jitter in the data stream. The
following paragraphs describe the test results obtained from the TNETA1555 for various performance
measurements.
Bellcore technical reference TR-TSY-000499 Issue 3, December 1989, page 7-1.
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