TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Low r
DS(on)
. . . 0.18
Typ at V
GS
= –10 V
3 V Compatible
Requires No External V
CC
TTL and CMOS Compatible Inputs
V
GS(th)
= –1.5 V Max
Available in Ultrathin TSSOP Package (PW)
ESD Protection Up to 2 kV Per
MIL-STD-883C, Method 3015
description
The
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of Texas
Instruments LinBiCMOS
process. With a
maximum V
GS(th)
of –1.5 V and an I
DSS
of only
0.5
μ
A, the TPS1100 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low r
DS(on)
and excellent ac
characteristics (rise time 10 ns typical) make the
TPS1100 the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated (PWM) controllers or
motor/bridge drivers.
TPS1100
is
a
single
P-channel
The ultrathin thin shrink small-outline package or
TSSOP (PW) version with its smaller footprint and
reduction in height fits in places where other
P-channel MOSFETs cannot. The size advantage
is especially important where board real estate is
at a premium and height restrictions do not allow
for a small-outline integrated circuit (SOIC)
package.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL OUTLINE
(D)
CHIP FORM
(Y)
TA
PLASTIC DIP
(P)
–40
°
C to 85
°
C
The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1100DR). The PW package is available only left-end taped and reeled
(indicated by the LE suffix on the device type; e.g., TPS1100PWLE). The chip form
is tested at 25
°
C.
TPS1100D
TPS1100PWLE
TPS1100Y
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright
1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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2
3
4
8
7
6
5
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
D OR PW PACKAGE
(TOP VIEW)
D PACKAGE
PW PACKAGE
SOURCE
DRAIN
GATE
ESD-
Protection
Circuitry
NOTE A: For all applications, all source pins should be connected
and all drain pins should be connected.
schematic