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參數(shù)資料
| 型號(hào)： | TPS2306DWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 427K |
| 代理商： | TPS2306DWG4 |
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TPS2306
DUAL SEQUENCING HOT SWAP POWER MANAGER
SLVS368 APRIL 2001
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
protecting the TPS2306 from voltage transients
Parasitic inductance associated with the power distribution can cause voltage spikes on the supply inputs if the
load current is suddenly interrupted by the TPS2306. It is important to limit the peak of these spikes to less than
15 V to prevent damage to the TPS2306. These spikes can be minimized by:
D Reducing power distribution inductance by locating the supply close to the plug-in module, maximizing the
width of high-current traces and using a PCB ground plane.
D Decoupling the VCC/CS1 and CS2 inputs with capacitors (C1 and C2 in Figure 2), located close to the
device. These capacitors are typically valued between 0.1
F and 1.0 F in a ceramic dielectric.
D Clamping the voltage at the VCC/CS1 and CS2 inputs with Zener diodes (D1 and D2 in Fig.2). The Zener
voltage of these devices can be selected according to the nominal input supply levels; however, the
maximum breakdown in all cases should be less than 15 V to avoid damage to the TPS2306.
D For applications with high trip currents or significant parasitic inductance, it may be necessary to install
additional bulk capacitance on the backplane side of the plug-in interface. These low-ESR capacitors
should be physically located close to the plug-in slot connector on the power rails. These devices have the
dual benefit of limiting the magnitude of spikes applied to the TPS2306, and limiting supply transients
propagated to other modules in the system if one of the protected outputs is interrupted.
layout considerations
Care should be taken to use good layout practice with the parts placement and etch routing of the plug-in PCB
to optimize the performance of the hot-swap circuit. Some of the key considerations are listed here.
D Decoupling capacitors should be located close to the device. Keep trace lengths from the capacitor to the
current sense input (CSx), and to the device GND pin to a minimum.
D Any protection devices (e.g., D1 and D2 in Figure 2) should be located close to the HSPM IC.
D Mount the charge pump reservoir capacitor (C3 in Figure 2) close to the device CPUMP pin.
D The reference current programming resistor (RREF in Figure 2) should be placed as close as feasible to the
device, with minimized trace length to the pin 4 output.
D To reduce insertion loss across the hot swap interface, use wide traces for the supply and return current
paths. A power plane can be used for the supply return or GND node.
D Additional copper placed at the land patterns of the sense resistors and pass FETs can significantly reduce
the thermal impedance of these devices, reducing temperature rise in the module and improving overall
reliability.
D Because typical values used for current-sense resistors can be so low (between <10 m and approximately
100 m
), board trace resistance between elements in the supply current paths becomes significant. To
achieve maximum accuracy of the constant-current thresholds, good Kelvin connections to the resistors
should be used for the IMAX and current sense inputs to the device (see Figure 4). The current sense traces
should connect symmetrically to the sense-resistor land pattern, in close proximity to the element leads,
not upstream or downstream from the device.
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