參數(shù)資料
型號: TPS2306DWG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝: SOIC-16
文件頁數(shù): 7/29頁
文件大?。?/td> 427K
代理商: TPS2306DWG4
TPS2306
DUAL SEQUENCING HOT SWAP POWER MANAGER
SLVS368 APRIL 2001
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 5. TPS2306 Typical IMAX1 Turnon
Sequence
t Time
I I
Input
Current
A
VI
Input
V
o
ltage
V
ENABLE
0
t0
20
40
60
80
100
120
140
2
3
4
5
6
1
0
t1
t2
IMAX1 Current
IREF = 100 A
t1 t2
t3
t4 t5
Figure 6. TPS2306 Slow Ramp Operation
GATE1
Output Voltage
t Time
V
O
Output
V
oltage
V
In Figure 5, the channel 1 ramp-up conditions are met at time t0 = 0. This means that the ENBL input is asserted,
both supply input and charge pump UVLO conditions are met, and the UP1 input voltage exceeds the 1.5-V
threshold. After a nominal delay, the IMAX1 current sink is turned on at t1, but only at a level that is approximately
5% of the programmed IMAX level. This stage typically lasts approximately 500
s. After about 500 s at t2, the
IMAX1 current ramps to the full programmed level (
IREF).
The same two-step characteristic is also used to turn-on the channel 2 FET.
From the load’s perspective, the slow turn-on of the pass elements has the effect shown in Figure 6.
Figure 6 shows the GATE1 and output voltage response to the typical IMAX1 ramp shown in Figure 5. In this
example, the FET is driving an RC-type load. At time t1, the IMAX1 input is turned on at a magnitude of ISNK/20.
The GATE1 output begins to drive the FET gate. However, the FET remains OFF initially, and no current is
allowed to flow. At t2 the gate voltage exceeds the VGS(on) threshold of the FET. Between t2 and t3 the output
current is limited to the slow turn-on level established by the TPS2306. Accordingly, only slight charging of the
output is obtained during this period. At t3, the slow ramp time period expires (the current at IMAX1 steps to the
programmed level) and the output now charges at a rate of IMAX/CLOAD1. As the output voltage approaches
the input supply level around time t4, the charging current begins to taper toward the steady-state load level.
The GATE1 output then drives towards the charge pump voltage, thus fully enhancing the external pass FET.
By time t5, the output has charged up to 95% of the input dc potential.
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