參數(shù)資料
型號： TPS2343DDPG3
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80
封裝： GREEN, PLASTIC, HTSSOP-80
文件頁數(shù)： 2/42頁
文件大?。?/td> 942K
代理商： TPS2343DDPG3
TPS2343
SLUS644B FEBRUARY 2005 MAY 2005
10
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NUMBER
NAME
I/O
DESCRIPTION
1
3VAUXGA
I/O
This pin is connected to the gate of the slot A 3VAUX internal power FET. Connect a capacitor from
this pin to PWRGND to program the slot A 3VAUX ramp rate. The recommended capacitor value is
22 nF for 0.23 V/ms ramp rate.
2
3VAUXA
O
This output supplies 3VAUX power to slot A when enabled and is pulled low by an internal FET
when there is a fault on slot A 3VAUX or when SWA is opened.
3
3VAUXI
I
Connect this power input to 3.3 V power to drive 3VAUX loads. Connect a 0.1-
F capacitor from
this pin to PWRGND.
4
3VAUXGB
I/O
This pin is connected to the gate of the slot B 3VAUX internal power FET. Connect a capacitor from
this pin to PWRGND to program the slot B 3VAUX ramp rate. The recommended capacitor value is
22 nF for 0.23 V/ms ramp rate.
5
3VAUXB
O
This output supplies 3VAUX power to slot B when enabled and is pulled low by an internal FET
when there is a fault on slot B 3VAUX or when SWB is opened.
6
3VGB
I/O
Gate drive for the 3-V slot B FET switch. Ramp rate is programmed by an external capacitor in
series with a 15-k
resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets
0.37 V/ms ramp rate.
7
3VISB
I
This pin in conjunction with the 3VSB pin senses the current to the 3.3-V slot B. It connects to the
load side of the 3.3-V current sense resistor. The recommended current sense resistor value is
6 m
. When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by an internal
FET. A 0.01-
F capacitor from this pin to ANAGND is recommended.
8
3VSB
I
This pin in conjunction with the 3VISB pin senses the current to the 3.3-V slot B main power load.
Connect to the source of the 3.3-V FET switch. A 0.01-
F capacitor from this pin to ANAGND is
recommended.
9
3VIOGB
I/O
Gate drive for the 3.3-V VIO slot B FET switches. Ramp rate is programmed by the external capaci-
tor connected from 3VIOGB to PWRGND. The recommended capacitor value is 22 nF for a 0.45
V/ms ramp rate.
10
PWRGND1
GND
Ground for high-current paths including discharge current of external gate capacitors.
11
15VIOGB
I/O
Gate drive for the 1.5-V VIO slot B FET switches. Ramp rate is programmed by the external capaci-
tor connected from 15VIOGB to PWRGND. The recommended capacitor value is 22 nF for a 0.45
V/ms ramp rate.
12
VIOISB
I
This pin in conjunction with the VIOSB pin senses the current to VIO slot B. It connects to the load
side of the VIO current sense resistor. The recommended current sense resistor value is 6 m.
When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by an internal FET.
A 0.01-
F capacitor from this pin to ANAGND is recommended.
13
VIOSB
I
This pin in conjunction with the VIOISB pin senses the current to VIO slot B. Connect to the current
sense resistor at the Vio FET switch. A 0.01-
F capacitor from this pin to ANAGND is recommen-
ded.
14
5VISB
I
This pin in conjunction with the 5VSB pin senses the current to the 5-V slot B main power load. It
connects to the load side of the 5-V current sense resistor. The recommended current sense resis-
tor value is 6 m
. When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by
an internal FET. A 0.01-
F capacitor from this pin to ANAGND is recommended.
15
5VSB
I
This pin in conjunction with the 5VISB pin senses the current to the 5-V slot B main power load. It
connects to the source of the 5-V FET switch. A 0.01-
F capacitor from this pin to ANAGND is re-
commended.
16
5VGB
I/O
Gate drive for the 5-V slot B FET switch. Ramp rate is programmed by an external capacitor in
series with a 15-k
resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets
0.37 V/ms ramp rate.
17
P12VINB
I
The 12-V power input to slot B. This input must be connected to P12VINA. Connect a 0.1-
F ca-
pacitor from this pin to PWRGND.
18
P12VGB
I/O
This pin is connected to the gate of the slot B 12-V internal power FET. Connect a capacitor from
this pin to PWRGND to program the slot B 12-V and 12-V power ramp rate. The recommended
capacitor value is 22 nF for 0.45 V/ms ramp rate on 12 V and a 0.68 V/ms ramp rate on 12-V pow-
er.
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