參數(shù)資料
型號： TPS2343DDPG3
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80
封裝： GREEN, PLASTIC, HTSSOP-80
文件頁數(shù)： 5/42頁
文件大?。?/td> 942K
代理商： TPS2343DDPG3
TPS2343
SLUS644B FEBRUARY 2005 MAY 2005
13
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NUMBER
NAME
I/O
DESCRIPTION
63
P12VGA
I/O
This pin is connected to the gate of the slot A 12-V internal power FET. Connect a capacitor from
this pin to PWRGND to program the slot A 12-V and 12-V power ramp rate. The recommended
capacitor value is 22 nF for 0.45-V/ms ramp rate on 12 V and a 0.68-V/ms ramp rate on 12-V pow-
er.
64
P12VINA
I
The 12-V power input to slot A. This input must be connected to P12VINB. Connect a 0.1-
F ca-
pacitor from this pin to PWRGND.
65
5VGA
I/O
Gate drive for the 5-V slot A FET switch. Ramp rate is programmed by an external capacitor in
series with a 15-
resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets
0.37-V/ms ramp rate.
66
5VSA
I
This pin in conjunction with the 5VISA pin senses the current to the 5-V slot A. It connects to the
source of the 5-V FET switch. A 0.01-
F capacitor from this pin to ANAGND is recommended.
67
5VISA
I
This pin in conjunction with the 5VSA pin senses the current to the 5-V slot A. It connects to the
load side of the 5-V current sense resistor. The recommended current sense resistor value is 6m
.
When PWRENA is false or FAULTA is true, this pin is discharged to PWRGND by an internal FET.
A 0.01-
F capacitor from this pin to ANAGND is recommended.
68
VIOSA
I
This pin in conjunction with the VIOISA pin senses the current to VIO slot A. Connect to the current
sense resistor at the Vio FET switch. A 0.01-
F capacitor from this pin to ANAGND is recommen-
ded.
69
VIOISA
I
This pin in conjunction with the VIOSA pin senses the current to VIO slot A. It connects to the load
side of the VIO current sense resistor. The recommended current sense resistor value is 6 m. VIO
bleed is connected to this pin. A 0.01-
F capacitor from this pin to ANAGND is recommended.
70
15VIOGA
I/O
Gate drive for the 1.5-V VIO slot A FET switches. Ramp rate is programmed by the external capaci-
tor connected from 15VIOGA to PWRGND. The recommended capacitor value is 22 nF for a
0.45-V/ms ramp rate.
71
PWRGND2
GND
Ground for high-current paths including discharge current of external gate capacitors.
72
V5IN
I
Connect this power input to 5-V power. This input is used to bias analog circuits. Connect a 0.1-
F
capacitor from this pin to PWRGND.
73
3VIOGA
I/O
Gate drive for the 3.3-V VIO slot A FET switches. Ramp rate is programmed by the external capaci-
tor connected from 3VIOGA to PWRGND. The recommended capacitor value is 22 nF for a 0.45-V/
ms ramp rate.
74
3VSA
I
This pin in conjunction with the 3VISA pin senses the current to the 3.3-V slot A main power load.
Connect to the source of the 3.3-V FET switch. A 0.01-
F capacitor from this pin to ANAGND is
recommended.
75
3VISA
I
This pin in conjunction with the 3VSA pin senses the current to the 3.3-V slot A. It connects to the
load side of the 3.3-V current sense resistor. The recommended current sense resistor value is
6 m
. When PWRENA is false or FAULTA is true, this pin is discharged to PWRGND by an internal
FET. A 0.01-
F capacitor from this pin to ANAGND is recommended.
76
3VGA
I/O
Gate drive for the 3.3-V slot A FET switch. Ramp rate is programmed by an external capacitor in
series with a 15-k
resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets
0.37-V/ms ramp rate.
77
PMEA
I
This input connects to the slot A power management event (PME) signal. This pin is internally
pulled up to 3VAUXA with a 100-k
resistor.
78
PMEOA
O
This output is connected to PMEA by a bus switch that is closed after slot A 3VAUX voltage is good
and opens immediately when there is a fault on slot A 3VAUX or SWA opens.
79
PMEOB
O
This output is connected to PMEB by a bus switch that is closed after slot B 3VAUX voltage is good
and opens immediately when there is a fault on slot B 3VAUX or SWB opens.
80
PMEB
I
This input connects to the slot B power management event (PME) signal. This pin is internally
pulled up to 3VAUXB with a 100-k
resistor.
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