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參數(shù)資料
| 型號： | TPS2343DDPG3 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80 |
| 封裝： | GREEN, PLASTIC, HTSSOP-80 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 942K |
| 代理商： | TPS2343DDPG3 |
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TPS2343
SLUS644B FEBRUARY 2005 MAY 2005
12
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NUMBER
NAME
I/O
DESCRIPTION
42
PLEDENA
I
This pin controls PWRLEDA. When this input is high, the LED is on (low).
43
ALEDENA
I
This pin controls ATTLEDA. When this input is high, the LED is on (low).
44
VIOSELA
I
This pin selects 3.3 V VIO for slot A when high, 1.5 V when low.
45
PWRLEDA
O
This output is an opendrain activelow power output that directly drives the slot A power indicator
LED. This pin indicates the slot A power LED output from PLEDENA. This signal pulls low with up
to 24 mA of drive when asserted and is pulled high by an on-chip 100-k
resistor to V5IN when
deasserted.
46
ATTLEDA
O
This open-drain power output directly drives the slot A attention indicator LED. This pin indicates
the slot A LED attention indicator output signal from ALEDENA. This signal pulls low with up to 24
mA of drive when asserted and is pulled high by an on-chip 100-k
resistor to V5IN when deas-
serted.
47
SWA
I
This input enables 3.3-V Aux power to slot A. When low, AUXFLTA is cleared. This pin has an inter-
nal 100-k
pull-up resistor to 3VAUXI and hysteresis.
48
PWRENA
I
This pin enables main power for slot A when high. When low, FAULTA is cleared and OUTUVA is
asserted. This pin has an internal 100-k
pull-up resistor to DIGVCC and hysteresis.
49
PWROFFA
O
This output is low when all of the slot A power outputs are discharged.
50
PCIXCAPA
I
This pin is the input to a 5-level A/D converter that determines the speed and mode of the inserted
A slot card based on the impedance from this pin to ANAGND. The operation of this pin meets the
specifications of the PCIX Local Bus Specification, revision 2.0.
51
PCIXCAP3A
O
This pin indicates bit 3 of the PCIXCAPA state.
52
OUTUVA
O
This opendrain output is low if slot A main outputs are below normal operating range. This pin has
an internal 100-k
pull-up resistor to DIGVCC.
53
AUXFLTA
O
This is an open-drain output that is low if there is a fault on VAUX power to slot A. This pin has an
internal 100-k
pull-up resistor to DIGVCC.
54
FAULTA
O
This is an open-drain output that is low if there is a fault on the main power to slot A. This pin has
an internal 100-k
pull-up resistor to DIGVCC.
55
PCIXCAP2A
O
This pin indicates bit 2 of the PCIXCAPA state.
56
DIGGND3
GND
This pin is the ground return for the digital circuits in the TPS2343.
57
PCIXCAP1A
O
This pin indicates bit 1 of the PCIXCAPA state.
58
PGOOD
I
This input is asserted when power is good in the whole system. This pin has an internal 100-k
pull-up resistor to DIGVCC and hysteresis.
59
ANAGND2
GND
Ground for low-level signals including the current sense circuits and the voltage reference.
60
M12VOA
O
This output delivers 12-V power to slot A when enabled and is pulled to PWRGND by an internal
FET when PWRENA is false or FAULTA is true. Turn-on of 12-V power tracks turn-on of 12-V
power and is controlled by the capacitor on P12VGA.
61
M12VINA
I
Connect this power input to 12-V power to drive slot A. This input must be connected to M12VINB.
Connect a 0.1-
F capacitor from this pin to PWRGND.
62
P12VOA
O
This output delivers 12-V power to slot A when enabled and is pulled to PWRGND by an internal
FET when PWRENA is false or FAULTA is true.
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