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參數(shù)資料
| 型號： | TPS2343DDPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 6-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO80 |
| 封裝： | GREEN, PLASTIC, HTSSOP-80 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 942K |
| 代理商： | TPS2343DDPR |
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TPS2343
SLUS644B FEBRUARY 2005 MAY 2005
33
www.ti.com
APPLICATION INFORMATION
Power Cycling and PME
The PCI power management specification defines a signal called PME (power management event) to allow
requests for power state changes to be communicated from the slot back to the system. The TPS2343 provides
a slot-specific PMEx input and a gated PMEOx output that can be monitored by the system. The gated PMEOx
output is enabled a delay after the SWx slot switch closes (SWx low) as shown in the timing diagram below. The
purpose of the delay is to ensure that 3.3-VAUX power is stable to the slot before connecting PMEx the signal.
If the PMEx signal was presented to the system while 3.3-VAUX power was still ramping up, a false trigger could result.The
3.3-VAUX circuitry provides over current fault detection. In the event of an over current fault on VAUX, the slot
3.3-VAUX and PME signals are immediately disconnected. The fault state is latched internally in the TPS2343
and is cleared either by opening the SWx slot switch or by removing the 3.3-VAUX power to the TPS2343.
PME ENABLE
10 ms
TYP
2.5 ms
TYP
10 ms
TYP
SWx
3VAUXx
Auxfltx
VAUX and PME Gating
When SWx is closed (low), 3VAUXx power is immediately applied to the slot with controlled slew rate, minimizing
inrush current into 3VAUXx bypass capacitors. After 3VAUXx power completes ramping up, a delay timer starts.
At the end of the delay timer cycle, the PMEx enable switches close, allowing connection of the PMEx signal
to the PMEOx output. Multiple PMEOx output pins can be connected to the same node, creating a PME bus
that can be connected to a master system interrupt input.When SWx is opened (high) or if there is a power fault
on slot x, the PMEx enable switch for that slot is immediately opened and the 3VAUXx power for that slot is
removed. Although these events happen at approximately the same time, the 3VAUXx power should remain
high until the PMEx switch is open so that falling 3VAUXx power does not cause a nuisance PMEx interrupt.
To insure that 3VAUXx remains high during a power fault, 3VAUXx should have a bypass capacitance of at least
20
F. If the capacitor is not available on the inserted card, it should be provided on the system board.The PME
circuit operates independently of any of the main power supplies.
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