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參數(shù)資料
| 型號(hào)： | TPS51020DBTR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | DUAL SWITCHING CONTROLLER, 450 kHz SWITCHING FREQ-MAX, PDSO30 |
| 封裝： | GREEN, PLASTIC, TSSOP-30 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 672K |
| 代理商： | TPS51020DBTR |
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TPS51020
SLUS564C JULY 2003 REVISED OCTOBER 2008
14
www.ti.com
APPLICATION INFORMATION
10-V N-CHANNEL FET BIAS or (VOUT1)/2 VTT VOLTAGE REFERENCE (REF_X)
TPS51020’s REF_X provides two functions depending on the operational mode. One is a linear regulator that
supply 10-V for FET switch biasing in the dual mode, the other is VTT reference voltage in the DDR mode.
If DDR is high ( > 2.2 V) then the REF_X output is a convenient 10-V, 2-mA (maximum) output, useful for biasing
N-channel FET switches typically used to manage S0, S3 and S5 sleep states where the main supply is switched
to many outputs. When VIN is < 12 V, REF_X approximately tracks VIN2 V.
If DDR is low, then the REF_X output becomes the VDDQ/2 (VO1_VDDQ/2) reference. This output is capable
of 5-mA source current and is left on even if channel two (VTT switcher) is turned off. REF_X is turned off if ENBL1
and ENBL2 are both low (see Table 2).
POWERGOOD
The TPS51020 has advanced powergood logic that allows single powergood circuit to monitor both SMPS
output voltages (see Figure 3 ).
VOUT1
VOUT2
PGOOD Delay Counter
PGOOD
ENBL1
ENBL2
Resets Delay Counter
t0
t1
t2
2048 c
Figure 3. PowerGood Timing Diagram
The PGOOD terminal is an open drain output. The PGOOD pin remains low until both power supplies have
started and have been in regulation (
±7.5%) for 2048 clock pulses.
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