參數(shù)資料
型號(hào)： TPS51020DBTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, 450 kHz SWITCHING FREQ-MAX, PDSO30
封裝： GREEN, PLASTIC, TSSOP-30
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 672K
代理商： TPS51020DBTR
TPS51020
SLUS564C JULY 2003 REVISED OCTOBER 2008
16
www.ti.com
APPLICATION INFORMATION
OVERCURRENT PROTECTION
Overcurrent protection (OCP) is achieved by comparing the drain to source voltage of the high-side and low-side
MOSFET to a set point voltage. This voltage appears at the TRIPx pin and is defined by the conversion voltage,
typically VIN, minus the I
× R drop of the ITRIP current flowing through the external resistor connected to the
conversion voltage. The offset of the internal comparators also plays a role in determining the overall accuracy
and set point of the OCP limit.
When the drain-to-source voltage of the synchronous MOSFET exceeds the set point voltage created by the
I
× R drop (usually 20 mV to around 150 mV), the synchronous MOSFET on-time is extended into the next pulse
and the high-side MOSFET OCP comparator is enabled. If during the subsequent high-side on-time the
drain-to-source voltage of the high-side MOSFET exceeds the set point voltage, then the high-side on-time
pulse is terminated. This low-side extension/high-side termination action has the effect of decreasing the output
voltage until the UVP circuit is activated to turn off both the high-side and low-side drivers. The TPS51020 ITRIP
current has a temperature coefficient of 4200 PPM/
°C.
The threshold voltage for the OCP comparator is set by I
× R drop across the trip resistor. The ITRIP current is
12.5-
A (typ) at R.T. so that the OCP point is given by following formula,
R
TRIP +
R
DS(on)
I
OCP )
I
RIPPLE
2
12.5
10*6
Precaution should be taken with board layout in order to design OCP point as desired. The conversion voltage
point must avoid high current path. Any voltage difference between the conversion point and VIN input for the
TPS51020 is included in the threshold voltage. VIN plane layout should consider the other channels
high-current path as well.
A brief discussion is required for TRIP2 function. When TRIP2 is connected, via a resistor to GND, only low-side
OCP is used. This is the case for cascade configuration been selected. In this mode, UVP does not play a roll
in the shut off action and there is only a short delay between the over current trigger level been hit and the power
MOSFETs turn off. However, as with UVP, the SSTRTx pins are discharged and both SMPS goes though a
restart.
LAYOUT CONSIDERATIONS
Below are some points to consider before the layout of the TPS51020 design begins.
D Signal GND and power GND should be isolated as much as possible, with a single point connection
between them.
D All sensitive analog components such as INV, SSTRT, SKIP, DDR, GND, REF_X, ENBL and PGOOD
should be reference to signal GND and be as short as possible.
D The source of low-side MOSFET, the Schottky diode anode, the output capacitor and OUTGND should be
referenced to power GND and be as short and wide as possible, otherwise signal GND is subject to the noise
of the outputs.
D PCB trace defined as the node of LL should be as short and wide as possible.
D Connections from the drivers to the gate of the power MOSFET should be as short and wide as possible
to reduce stray inductance and the noise at the LL node.
D The drain of high-side MOSFET, the input capacitor and the trip resistor should be as short and wide as
possible. For noise reduction, a 22-pF capacitor CTRIP can be placed in parallel with the trip resistor.
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