參數(shù)資料
型號(hào)： TPS54010PWPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝： GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 984K
代理商： TPS54010PWPG4
www.ti.com
SLOW-START/ENABLE (SS/ENA)
+
PVIN
VBIAS
SS/ENA
10 k
10 k
27.4 k
100 k
VIN
1/2 LM293
MAXIMUM OUTPUT VOLTAGE
V
O(max) +
PVIN
(min)
0.9
(24)
GROUNDING AND PowerPAD LAYOUT
t
d +
C
(SS)
1.2 V
5 mA
(25)
t
(SS) +
C
(SS)
0.7 V
5 mA
(26)
VBIAS REGULATOR (VBIAS)
UNDERVOLTAGE LOCKOUT (UVLO)
TPS54010
SLVS509B – MAY 2004 – REVISED JUNE 2005
the UVLO comparator, and a 2.5-ms rising and falling
edge deglitch circuit reduce the likelihood of shutting
the device down due to noise on VIN. UVLO is with
respect to VIN and not PVIN, see the Application
Information section.
The slow-start/enable pin provides two functions.
Figure 35. Undervoltage Lockout Circuit for PVIN
Using Open-Collector or Open-Drain Comparator
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage ex-
ceeds the start threshold voltage of approximately
PVIN and VIN can be tied together for 3.3-V bus
1.2 V. When SS/ENA exceeds the enable threshold,
operation.
device start-up begins. The reference voltage fed to
the error amplifier is linearly ramped up from 0 V to
0.891 V in 3.35 ms. Similarly, the converter output
The maximum attainable output voltage is limited by
voltage reaches regulation in approximately 3.35 ms.
the minimum voltage at the PVIN pin. Nominal
Voltage hysteresis and a 2.5-ms falling edge deglitch
maximum duty cycle is limited to 90% in the
circuit reduce the likelihood of triggering the enable
TPS54010; so, maximum output voltage is:
due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with
Care must be taken while operating when nominal
a low-value capacitor connected between SS/ENA
conditions cause duty cycles near 90%. Load transi-
and AGND.
ents can require momentary increases in duty cycle.
Adding a capacitor to the SS/ENA pin has two effects
If the required duty cycle exceeds 90%, the output
on start-up. First, a delay occurs between release of
may fall out of regulation.
the SS/ENA pin and start-up of the output. The delay
is proportional to the slow-start capacitor value and
lasts until the SS/ENA pin reaches the enable
The TPS54010 has two internal grounds (analog and
threshold. The start-up delay is approximately:
power). Inside the TPS54010, the analog ground ties
to all of the noise-sensitive signals, whereas the
power ground ties to the noisier power signals. The
PowerPAD must be tied directly to AGND. Noise
Second, as the output becomes active, a brief
injected between the two grounds can degrade the
ramp-up at the internal slow-start rate may be ob-
performance of the TPS54010, particularly at higher
served before the externally set slow-start rate takes
output currents. However, ground noise on an analog
control and the output rises at a rate proportional to
ground plane can also cause problems with some of
the slow-start capacitor. The slow-start time set by
the control and bias signals. For these reasons,
the capacitor is approximately:
separate analog and power ground planes are rec-
ommended. These two planes must tie together
directly at the IC to reduce noise between the two
grounds. The only components that must tie directly
The actual slow-start time is likely to be less than the
to the power ground plane are the input capacitor, the
above approximation due to the brief ramp-up at the
output capacitor, the input voltage decoupling capaci-
internal rate.
tor, and the PGND pins of the TPS54010.
The VBIAS regulator provides internal analog and
The TPS54010 incorporates an undervoltage-lockout
digital blocks with a stable supply voltage over
circuit to keep the device disabled when the input
variations in junction temperature and input voltage. A
voltage (VIN) is insufficient. During power up, internal
high-quality, low-ESR, ceramic bypass capacitor is
circuits are held inactive until VIN exceeds the
required on the VBIAS pin. X7R or X5R grade
nominal UVLO threshold voltage of 2.95 V. Once the
dielectrics are recommended because their values
UVLO start threshold is reached, device start-up
are more stable over temperature. The bypass ca-
begins. The device operates until VIN falls below the
pacitor must be placed close to the VBIAS pin and
nominal UVLO stop threshold of 2.8 V. Hysteresis in
returned to AGND.
20
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