參數(shù)資料
型號(hào): TPS54010PWPG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: 25 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝: GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù): 28/29頁(yè)
文件大?。?/td> 984K
代理商: TPS54010PWPG4
www.ti.com
APPLICATION INFORMATION
PCB LAYOUT
COMPENSATION
NETWORK
BOOT
CAPACITOR
VOUT
OUTPUT INDUCTOR
PH
OUTPUT
FILTER
CAPACITOR
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
SYNC
SS/ENA
VBIAS
VIN
PVIN
PGND
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
SLOW-START
CAPACITOR
BIAS CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
EXPOSED
POWERPAD
AREA
TOPSIDE GROUND AREA
VIA to GROUND PLANE
TPS54010
SLVS509B – MAY 2004 – REVISED JUNE 2005
Figure 10. TPS54010 Layout
The PVIN pins are connected together on the printed-
wide trace for the analog ground signal path. This
circuit board (PCB) and bypassed with a low ESR
analog ground is used for the voltage set point
ceramic bypass capacitor. Care should be taken to
divider, timing resistor RT, slow-start capacitor, and
minimize the loop area formed by the bypass capaci-
bias capacitor grounds. The PH pins are tied together
tor connections, the PVIN pins, and the TPS54010
and routed to the output inductor. Because the PH
ground pins. The minimum recommended bypass
connection is the switching node, an inductor is
capacitance is a 10-F ceramic capacitor with a X5R
located close to the PH pins, and the area of the PCB
or X7R dielectric. The optimum placement is as close
conductor is minimized to prevent excessive capaci-
as possible to the PVIN pins, the AGND, and PGND
tive coupling. Connect the boot capacitor between the
pins. See Figure 10 for an example of a board layout.
phase node and the BOOT pin as shown in Fig-
If the VIN is connected to a separate source supply, it
ure 10. Keep the boot capacitor close to the IC, and
is bypassed with its own capacitor. There is an area
minimize the conductor trace lengths. Connect the
of ground on the top layer of the PCB, directly under
output filter capacitor(s) between the VOUT trace and
the IC, with an exposed area for connection to the
PGND. It is important to keep the loop formed by the
PowerPAD. Use vias to connect this ground area to
PH pins, Lout, Cout, and PGND as small as is
any internal ground planes. Use additional vias at the
practical. Place the compensation components from
ground side of the input and output filter capacitors.
the VOUT trace to the VSENSE and COMP pins. Do
The AGND and PGND pins are tied to the PCB
not place these components too close to the PH
ground by connecting them to the ground area under
trace. Due to the size of the IC package and the
the device as shown in Figure 10. Use a separate
device pinout, they must be routed close, but main-
8
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