參數(shù)資料
型號(hào)： TPS65185RSLT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 0.4 MM PITCH, 0.9 MM HEIGHT, PLASTIC, VQFN-48
文件頁(yè)數(shù)： 15/49頁(yè)
文件大小： 2488K
代理商： TPS65185RSLT
PRODUCTPREVIEW
SLVSAQ8A
– FEBRUARY 2011 – REVISED MAY 2011
FAULT HANDLING AND RECOVERY
The TPS65185 monitors input and output voltages and die temperature and will take action if operating
conditions are outside normal limits. Whenever the TPS65185 encounters:
Thermal Shutdown (TSD)
Positive Boost Under Voltage (VB_UV)
Inverting Buck-Boost Under Voltage (VN_UV)
Input Under Voltage Lock Out (UVLO)
it shuts down all power rails and enters STANDBY mode. Shut-down follows the order defined by DWNSEQx
registers. The exception is VCOM fault witch leads to immediate shutdown of all rails. Once a fault is detected,
the PWR_GOOD and nINT pins are pulled low and the corresponding interrupt bit is set in the interrupt register.
Power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the INT1 and INT2
register. Alternatively, toggling the WAKEUP pin also resets the interrupt bits. As the PWRUP input is edge
sensitive, the host must toggle the PWRUP pin to re-enable the rails through GPIO control, i.e. it must bring the
PWRUP pin low before asserting it again. Alternatively rails can be re-enbled through the I2C interface.
Whenever the TPS65185 encounters under-voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV)
or VDDH (VDDH_UV), rails are not shut down but the PWR_GOOD and nINT is pulled low with the
corresponding interrupt bit set. The device remains in ACTIVE mode and recovers automatically once the fault
has been removed.
POWER GOOD PIN
The power good pin (PWR_GOOD) is an open drain output that is pulled high (by an external pull-up resistor)
when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails
encounters a fault or is disabled. PWR_GOOD remains low if one of the rails is not enabled by the host and only
after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).
INTERRUPT PIN
The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT1 or INT2 bits
are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit
has been read by the host. If the fault persists, the nINT pin will be pulled low again after a maximum of 32
s.
Interrupt events can be masked by re-setting the corresponding enable bit in the INT_EN1 and INT_EN2 register,
i.e. the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits
affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT1/INT2 bits
themselves.
Note that persisting faults such as thermal shutdown can cause the nINT pin to be pulled low for an extended
period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set
the corresponding mask bit after receiving the interrupt and keep polling the INT1/INT2 register to see when the
fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
PANEL TEMPERATURE MONITORING
The TPS65185 provides circuitry to bias and measure an external Negative Temperature Coefficient Resistor
(NTC) to monitor the display panel temperature in a range from -10
°C to 85°C with and accuracy of ±1°C from
0
°C to 50°C. Temperature measurement must be triggered by the controlling host and the last temperature
reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the
programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed
by more than a user-defined threshold from the baseline value. Details are explained under
“HOT, COLD, and
temperature-change interrupts
”.
22
Copyright
2011, Texas Instruments Incorporated
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