參數(shù)資料
型號(hào): TPS65185RSLT
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PQCC48
封裝: 6 X 6 MM, 0.4 MM PITCH, 0.9 MM HEIGHT, PLASTIC, VQFN-48
文件頁數(shù): 18/49頁
文件大?。?/td> 2488K
代理商: TPS65185RSLT
PRODUCTPREVIEW
SLAVE ADDRESS
W A
REG ADDRESS
A
SLAVE ADDRESS
R A
DATA REGADDR
A
S
DATA REGADDR +n
A
DATA REGADDR +n+1
P
From master to slave
From slave to master
S
W
A
P
Start
Write (low)
Acknowlege
Stop
R Read (high)
S
Not Acknowlege
n bytes + ACK
SLAVE ADDRESS
W A
REG ADDRESS
A
DATA REGADDR
A
S
DATA SUBADDR +n
A
DATA SUBADDR +n+1
P
n bytes + ACK
S
1-7
8
9
1-7
8
9
1-7
8
9
P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/
nACK
STOP
START
SDA
SCL
tf
tHD;STA
tLOW
tr
tHD;DAT
tSU;DAT
tHIGH
tSU;STA
tHD;STA
tSP
tSU;STO
tr
tBUF
tf
S
Sr
S
P
SDA
SCL
SLVSAQ8A
– FEBRUARY 2011 – REVISED MAY 2011
reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the
SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the
low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and
data words. The I2C interfaces will auto-sequence through register addresses, so that multiple data words can be
sent for a given I2C transmission. Reference Figure 29 and Figure 30 for deail.
TOP: Master writes data to slave.
BOTTOM: Master reads data from slave.
Figure 29. I2C Data Protocol
Figure 30. I2C Start/Stop/Acknowledge Protocol
Figure 31. I2C Data Transmission Timing
Copyright
2011, Texas Instruments Incorporated
25
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