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參數資料
| 型號： | TS68230 |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數： | 15/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230 |
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5. H2(H4) may be an output pin in the pulsed out-
put handshake protocol. It is asserted exactly
as in the interlocked output protocol above, but
never remains asserted longer than four clock
cycles. Typically, a four clock pulse is genera-
ted. But in the case that a subsequent H1(H3)
asserted edge occurs before termination of the
pulse, H2(H4) is negated asynchronously,
thus shortening the pulse. The H2S(H4S) sta-
tus bit is always zero. When H12 enable (H34
enable) is zero, H2(H4) is held negated.
A sample timing diagram is shown in figure 2.2. The
H2(H4) interlocked and pulsed output handshake
protocols are shown. The DMAREQ pin is also
shown assuming it is enabled. All handshake pin
sense bits are assumed to be zero ; thus, the pins
are in the low state when asserted. Due to the great
similarity between modes, this timing diagram is ap-
plicable to all double-buffered output transfers.
2.2. REQUESTING BUS MASTER SERVICE
The PI/T has several means of indicating a need for
service by a bus master. First, the processor may
poll the port status register. It contains a status bit
for each handshake pin, plus a level bit that always
reflects the instantaneous state of that handshake
pin. A status bit is one when the PI/T needs servicing
(i.e., generally when the bus master needs to read
or write data to the ports) or when a handshake pin
used as a simple status input has been asserted.
The interpretation of these bits is dependent on the
chosen mode and submode.
Second, the PI/T may be placed in the processor’s
interrupt structure. As mentioned previously, the
PI/T contains port A and B control registers that
configure the handshake pins. Other bits in these re-
gisters enable an interrupt associated with each
handshake pin. This interrupt is made available
through the PC5/PIRQ pin, if the PIRQ function is
selected. Three additional conditions are required
for PIRQ to be asserted : 1) the handshake pin sta-
tus bit is set, 2) the corresponding interrupt (service
request) enable bit is set, and 3) DMA requests are
not associated with that data transfer (H1 and H3
only). The conditions from each of the four hand-
shake status bits and corresponding status bits are
ORed to determine PIRQ. To clear the interrupt, the
proper status bit must be cleared (see
2.3. Direct
Method of Resetting Status
).
The third method of requesting service is via the
PC4/DMAREQ pin. This pin can be associated with
double-buffered transfers in each mode. If it is used
as a DMA controller request, it can initiate requests
to keep the PI/T’s input/output double-buffering
empty/full as much as possible. It will not overrun the
DMA controller. The pin is compatible with the
68440 direct memory access controller (DMAC).
2.2.1. VECTORED, PRIORITIZED PORT INTER-
RUPTS. Use of TS68000 compatible vectored inter-
rupts with the PI/T requires the PIRQ and PIACK
pins. When PIACK is asserted while PIRQ is asser-
ted, the PI/T places an 8-bit vector on the data pins
D0-D7. Under normal conditions, this vector corres-
ponds to the highest priority enabled active port in-
terrupt source with which the DMAREQ pin is not
currently associated. The most-significant six bits
are provided by the port interrupt vector register
(PIVR), with the lower two bits supplied by prioriti-
zation logic according to conditions present when
PIACK is asserted. It is important to note that the on-
Figure 2.2 :
Double-Buffered Output Transfers Timing Diagram.
TS68230
15/61
相關PDF資料 |
PDF描述 |
|---|---|
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230P | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68302DESC01QYA | Integrated Multiprotocol Processor IMP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS68230CFN10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | 制造商:STME 功能描述: |
| TS68230CP8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
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