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參數(shù)資料
| 型號： | TS68230 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時(shí)器 |
| 文件頁數(shù)： | 44/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230 |
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8. For configurations in which the prescaler is not u-
sed, the contents of the counter preload registers
are transferred to the counter on the first asserted
edge of the TIN input after entering the run state.
On subsequent asserted edges the counter de-
crements, rolls over, or is loaded from the counter
preload registers.
9. The smallest value allowed in the counter preload
register for use with the counter is $000001.
5.1.3. TIMER INTERRUPT ACKNOWLEDGE CY-
CLES. Several conditions may be present when the
timer interrupt acknowledge pin (TIACK) is asser-
ted. These conditions affect the PI/T’s response and
the termination of the bus cycle (see table 5.1).
5.2. TIMER APPLICATIONS SUMMARY
The following paragraphs outline programming of the
timer control register for several typical examples.
5.2.1.PERIODIC INTERRUPT GENERATOR
EXAMPLE.
7
6
5
4
In this configuration the timer generates a periodic
interrupt. The TOUT pin is connected to the sys-
tem’s interrupt request circuitry and the TIACK pin
may be used as an interrupt acknowledge input to
the timer. The TIN pin may be used as a clock input.
The processor loads the counter preload registers
(CPR) and timer control register (TCR), and then
enables the timer. When the 24-bit counter passes
from $000001 to $000000, the ZDS status bit is set
and the TOUT (interrupt request) pin is asserted. At
the next clock to the 24-bit counter, it is again loaded
with the contents of the CPRs and thereafter decre-
ments. In normal operation, the processor must di-
rect clear the status bit to negate the interrupt re-
quest (see figure 5.1).
5.2.2. SQUARE WAVE GENERATOR.
In this configuration the timer produces a square
7
6
5
4
wave at the TOUT pin. The TOUT pin is connected
to the user’s circuitry and the TIACK pin is not used.
The TIN pin may be used as a clock input.
The processor loads the counter preload registers
and timer control register, and then enables the ti-
mer. When the 24-bit counter passes form $000001
to $000000 the ZDS status bit is set and the TOUT
(square wave output) pin is toggled. At the next clock
to the 24-bit counter it is again loaded with the
contents of the CPRs, and thereafter decrements. In
this application there is no need for the processor to
direct clear the ZDS status bit ; however, it is possi-
ble for the processor to sync itself with the square
wave by clearing the ZDS status bit, then polling it.
The processor may also read the TOUT level at the
port C address.
Note that the PC3/TOUT pin functions as PC3 fol-
lowing the negation of RESET. If used in the square
wave configuration, a pullup resistor may be requi-
red to keep a known level prior to programming.
Prior to enabling the timer, TOUT is high (see fig-
ure 5.2).
3
2
1
0
Timer
Enable
TOUT/TIACK
Control
*
Z.D
Control
Clock
Control
1
x
1
0
0
00 or 1X Changed
3
2
1
0
Timer
Enable
TOUT/TIACK
Control
*
Z.D.
Control
Clock
Control
1
x
1
1
0
00 or 1X Changed
Table 5.1 :
Response to Timer Interrupt Acknowledge
PC3/TOUT Function
Response to Asserted TIACK
No Response
No DTACK
No Response
No DTACK
No Response
No DTACK
Timer Interrupt Vector Contents DTACK Asserted
PC3 - Port C Pin
TOUT - Square Wave
TOUT - Negated Timer Interrupt Request
TOUT - Asserted Timer Interrupt Request
TS68230
44/61
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| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
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| TS68230CFN10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
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| TS68230FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
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