參數(shù)資料
型號(hào)： TS68230
廠商： 意法半導(dǎo)體
英文描述： HMOS PARALLEL INTERFACE/TIMER
中文描述： HMO的并行接口/定時(shí)器
文件頁(yè)數(shù)： 39/61頁(yè)
文件大小： 2911K
代理商： TS68230
Bits 2, 1, and 0 determine port interrupt priority. The
priority as shown in table 4.2 is in descending order
left to right.
4.3. PORT DATA DIRECTION REGISTERS
The following paragraphs describe the port data di-
rection registers.
4.3.1. PORT A DATA DIRECTION REGISTER
(PADDR). The port A data direction register deter-
mines the direction and buffering characteristics of
each of the port A pins. One bit in the PADDR is as-
signed to each pin. A zero indicates that the pin is
used as a input, while a one indicates it is used as
an output. The PADDR is always readable and wri-
table. This register is ignored in mode 3.
All bits are reset to the zero (input) state when the
RESET pin is asserted.
4.3.2. PORT B DATA DIRECTION REGISTER
(PBDDR). The PBDDR is identical to the PADDR for
the port B pins and the port B data register, except
that this register is ignored in modes 2 and 3.
4.3.3. PORT C DATA DIRECTION REGISTER
(PCDDR). The port C data direction register speci-
fies whether each dual-function pin that is chosen for
port C operation is an input (zero) or an output (one)
pin. The PCDDR, along with bits that determine the
respective pin’s function, also specify the exact
hardware to be accessed at the port C data register
address (see
4.6.3. Port C Data Register
(PCDR)
for more details). The PCDDR is an 8-bit register
that is readable and writable at all times. Its opera-
tion is independent of the chosen PI/T mode.
These bits are cleared to zero when the RESET pin
7
6
5
4
3
is asserted.
4.4. PORT INTERRUPT VECTOR REGISTER
(PIVR)
The port interrupt vector register contains the upper
order six bits of the four port interrupt vectors. The
contents of this register may be read two ways : by
an ordinary read cycle, or by a port interrupt acknow-
ledge bus cycle. The exact data read depends on
how the cycle was initiated and other factors. Beha-
vior during a port interrupt acknowledge cycle is
summarized in table 2.1.
From a normal read cycle, there is never a conse-
quence to reading this register. Following negation of
the RESET pin, but prior to writing to the PIVR, a $0F
will be read. After writing to the register, the upper six
bits may be read and the lower two bits are forced to
zero. No prioritization computation is performed.
4.5. PORT CONTROL REGISTERS (PACR,
PBCR)
The port A and B control registers (PACR and
PBCR) are described in
Section 3 Port Modes.
The
description is organized such that for each
mode/submode all programmable options of each
pin and status bit are given.
4.6. PORT DATA REGISTERS
The following paragraphs describe the port data re-
gisters.
4.6.1. PORT A DATA REGISTER (PADR). The port
A data register is a holding register for moving data
to and from the port A pins. The port A data direction
register determines whether each pin is an input (ze-
ro) or an output (one), and is used in configuring the
actual data paths. The data paths are described in
Section 3 Port Modes.
This register is readable and writable at all times.
Depending on the chosen mode/submode, reading
or writing may affect the double-buffered handshake
mechanism. The port A data register is not affected
by the assertion of the RESET pin.
4.6.2. PORT B DATA REGISTER (PBDR). The port
B data register is a holding register for moving data
to and from port B pins. The port B data direction re-
gister determines whether each pin is an input (zero)
or an output (one), and is used in configuring the ac-
tual data paths. The data paths are described in
Section 3 Port Modes
.
This register is readable and writable at all times.
Depending on the chosen mode/submode, reading
or writing may affect the double-buffered handshake
mechanism. The port B data register is not affected
by the assertion of the RESET pin.
4.6.3. PORT C DATA REGISTER (PCDR). The port
C data register is a holding register for moving data
to and from each of the eight port C/ alternate-func-
tion pins. The exact hardware accessed is determi-
ned by the type of bus cycle (read or write) and
individual conditions affecting each pin. These
conditions are : 1) whether the pin is used for the port
C or alternate function, and 2) whether the port C da-
2
1
0
*
Interrupt Vector Number
*
TS68230
39/61
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