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參數(shù)資料
| 型號： | TS68230 |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 28/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230 |
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PBCR
5 4 3
0 X X
1 0 0
1 0 1 Output pin - asserted, H4S is always cleared.
1 1 0
Output pin - interlocked input handshake protocol.
1 1 1
Output pin - pulsed input handshake protocol.
H4 Control
Input pin - edge-sensitive status input, H4S is set on an asserted edge.
Output pin - negated, H4S is always cleared.
PBCR
2
0
1
H2 Interrupt Enable
The H4 interrupt is disabled.
The H4 interrupt is enabled.
PBCR
1
0
1
H3 SVCRQ Enable
The H3 interrupt and DMA request are disabled.
The H3 interrupt and DMA request are enabled.
PBCR
0
X
H3 Status Control
The H3S status bit is set anytime input data is present in the double-buffered input path.
3.4.4. SUBMODE X1 - PIN-DEFINABLE DOUBLE-
BUFFERED OUTPUT OR NON-LATCHED INPUT.
In mode 1 submode X1, double-buffered output
transfers of up to 16 bits may be obtained. Data is
written by the bus master (processor or DMA con-
troller) in two bytes. The first byte (most significant)
is written to the port A data register. It is stored in a
temporary latch until the next byte is written to the
port B data register. Then all 16 bits are transferred
to one of the output latches of ports A and B. The
DMAREQ pin may be used to signal a DMA control-
ler to transfer another word to the port output
latches. (The 68440 DMAC can be programmed to
perform the exact transfers needed for compatibility
with the PI/T.) H4 may be programmed as :
1. H4 may be an edge-sensitive status input that
is independent of H3 and the transfer of port
data. On the asserted edge of H4, the H4S sta-
tus bit is set. It is cleared by either the RESET
pin being asserted, writing a one to the parti-
cular status bit in the port status register (PSR),
or when the H34 enable bit of the port general
control register is clear.
2. H4 may be a general-purpose output pin that
is always negated. In this case the H4S status
bit is always clear.
3. H4 may be a general-purpose output pin that
is always asserted. In this case the H4S status
bit is always clear.
4. H4 may be an output pin in the interlocked out-
put handshake protocol. H4 is asserted two
clock cycles after data is transferred to the dou-
ble-buffered output latches. The data remains
stable at the port pins and H4 remains asser-
ted until the next asserted edge of the H3 input.
At that time, H4 is asynchronously negated. As
soon as the next data is available, it is trans-
ferred to the output latches. When H4 is nega-
ted, asserted transitions of H3 have no affect
on data paths. The H4S status bit is always
clear. When H34 enable is clear, H4 is held ne-
gated.
5. H4 may be an output pin in the pulsed output
handshake protocol. It is asserted exactly as in
the interlocked protocol above, but never re-
mains asserted longer than four clock cycles.
Typically, a four clock pulse is generated. But
in the case that a subsequent H3 asserted
edge occurs before termination of the pulse,
H4 is negated asynchronously shortening the
pulse. The H4S status bit is always cleared.
When H34 enable is clear, H4 is held negated.
Programmable Options Mode 1 - Port A Submode XX and Port B Submode X0
(continued)
TS68230
28/61
相關PDF資料 |
PDF描述 |
|---|---|
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230P | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68302DESC01QYA | Integrated Multiprotocol Processor IMP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TS68230CFN10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230CFN8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | 制造商:STME 功能描述: |
| TS68230CP8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
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