參數(shù)資料
型號(hào): TS8308500CGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68
封裝: 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68
文件頁(yè)數(shù): 31/50頁(yè)
文件大?。?/td> 491K
代理商: TS8308500CGL
37
TS8308500
2193A–BDC–04/03
Package
Description
Table 7. TS8308500 Pad Description
Pad number
Chip Pad Name
Chip Pad Function
1VPLUSD
Positive digital supply (double pad)
(2)
2D5
In-phase (+) digital output, bit 5
(D7 is the MSB; Bit 7, D0 is the LSB; Bit 0)
3
D5B
Inverted phase (-) digital output, bit 5
4
D4
In-phase (+) digital output, bit 4
5
D4B
Inverted phase (-) digital output, bit 4
6DVEE
-5V digital supply (double pad)
7
DR
In-phase (+) Data Ready
8
DRB
Inverted phase (-) Data Ready
9
D3
In-phase (+) digital output, bit 3
10
D3B
Inverted phase (-) digital output, bit 3
11
V
PLUSD
Positive digital supply (double pad)
(2)
12
D2
In-phase (+) digital output, bit 2
13
D2B
Inverted phase (-) digital output, bit 2
14
D1
In-phase (+) digital output, bit 1
15
D1B
Inverted phase (-) digital output, bit 1
16
D0
In-phase (+) digital output, bit 0, Least Significant Bit
17
D0B
Inverted phase (-) digital output, bit 0, Least Significant Bit
18
GORG
Gray or Binary data output format select
(1)
19
V
CC
+5V supply (double pad)
20
GND
Analog ground (double pad)
21
VCC
+5V supply (double pad)
22
V
EE
-5V analog supply (double pad)
23
V
CC
+5V supply (double pad)
24
GND
Analog ground (double pad)
25
CLK
In-phase (+) clock input (double pad)
26
GND
Analog ground
27
CLKB
Inverted phase (-) clock input (double pad)
28
GND
Analog ground (double pad)
29
V
EE
-5V analog supply (double pad)
30
V
CC
+5V supply (double pad)
31
V
EE
-5V analog supply (double pad)
32
DIOD/DRRB
Diode input for Tj monitoring/Input for asynchronous Data Ready Reset
33
GND
Analog ground
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