參數(shù)資料
型號(hào): TS83102G0BVGL
廠商: E2V TECHNOLOGIES PLC
元件分類(lèi): ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁(yè)數(shù): 25/60頁(yè)
文件大?。?/td> 1510K
代理商: TS83102G0BVGL
31
0830E–BDC–06/07
e2v semiconductors SAS 2007
TS83102G0B
Without ADC input referred thermal noise:
ENOB = 9.2 bits
SINAD = 57 dB
THD = -55.7 dB (over 25 harmonics)
SFDR = -62.6 dBc
SNR = 57.3 dB
Conclusion:
Though the ENOB is 7.6 bits (in this example at 1.4 Gsps Nyquist conditions), the ADC features a 10-bit
linearity regarding the 60 dB typical SFDR performance.
However, it has to be pointed out that the ENOB is actually limited by the ADC’s input referred thermal
noise, which dominates the rms quantization noise. For certain applications (using a spread spectrum)
the signal may be recovered below the thermal noise floor (by cross correlation since it is white noise).
Therefore, the thermal noise can be extracted from the ENOB: the ENOB without a referred input ther-
mal noise is 9.2 instead of 7.6 in this example, only limited by the quantization noise and clock induced
jitter.
11. Equivalent Input/Output Schematics
Figure 11-1. Equivalent Analog Input Circuit and ESD Protections
1 mA
VE
E
=
-
5
V
Die Pads
VIN
VINB
Termination
Resistors
Soldered into
the Package
Cavity
50
2%
GND
50
2%
Package
Pins
ESD
120 fF
VEE = -5V
1.
5V
VEE = -5V
ESD
120 fF
50
Controlled
Transmission Line
(Bonding + Package + Ball)
Double Pad
260 fF
50
Controlled
Transmission Line
(Bonding +
Package + Ball)
Double Pad
260 fF
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