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參數(shù)資料
| 型號(hào)： | TS83102G0BVGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 1510K |
| 代理商： | TS83102G0BVGL |
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34
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
Figure 11-6. DRRB Equivalent Input Schematics and ESD Protections
12. Definition of Terms
200
10 k
GND
DRRB
GND
VEE = -5V
-1.3V
-2.6V
200
A
200
Α
PAD
130 fF
ESD
65 fF
ESD
75 fF
Table 12-1.
Definitions of Terms
Term
Description
BER
Bit Error Rate
Probability to exceed a specified error threshold for a sample. An error code is a code that
differs by more than ±4 LSB from the correct code
BW
Full-power Input
Bandwidth
The analog input frequency at which the fundamental component in the digitally
reconstructed output has fallen by 3 dB with respect to its low frequency value (determined
by FFT analysis) for input at full-scale
DG
Differential Gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20% full-
scale peak to peak amplitude. F
IN = 5 MHz (TBC)
DNL
Differential Non-
linearity
The differential non-linearity for an output code (i) is the difference between the measured
step size of code (i) and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the
maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that
there are no missing output codes and that the transfer function is monotonic
DP
Differential Phase
The peak phase variation (in degrees) at five different DC levels for an AC signal of 20% full-
scale peak to peak amplitude. F
IN = 5 MHz (TBC)
FS MAX
Maximum Sampling
Frequency
Sampling frequency for which ENOB < 6 bits
FS MIN
Minimum Sampling
Frequency
Sampling frequency for which the ADC gain has fallen by 0.5 dB with respect to the gain
reference value. Performances are not guaranteed below this frequency
FPBW
Full Power Input
Bandwidth
Analog input frequency at which the fundamental component in the digitally reconstructed
output waveform has fallen by 3 dB with respect to its low frequency value (determined by
FFT analysis) for input at full-scale -1 dB (-1 dBFS)
ENOB
Effective Number of
Bits
Where A is the actual input amplitude and V is the
full-scale range of the ADC under test
IMD3
Inter Modulation
Distortion
The two tones third order intermodulation distortion (IMD3) rejection is the ratio of either
input tone to the worst third order intermodulation products
ENOB
SINAD
1,76
–
20
A
Fs 2
-------------
log
+
6,02
------------------------------------------------------------------------
=
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS83102G0CGL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog to Digital Converter |
| TS83102G0GSZR5 | 制造商:e2v technologies 功能描述:TS83102G0GSZR5 - Trays |
| TS831-3I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MICROPOWER VOLTAGE SUPERVISOR RESET ACTIVE LOW |
| TS831-3ID | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TS831-3IDT | 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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