參數(shù)資料
型號： TS83102G0BVGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝： 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁數(shù)： 6/60頁
文件大小： 1510K
代理商： TS83102G0BVGL
14
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
8.
TS83102G0B Package Description
Table 8-1.
Pin Description (CBGA 152)
Symbol
Pin Number
Function
Power Supplies
VCC, VCCTH
K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8, R8
5V analog supply (connected to same power supply
plane)
GND
B1, C1, D1, G1, M1, Q1, B2, C2, D2, E2, F2,
G2, N2, P2, Q2, A3, B3, D3, E3, F3, G3, N3, P4,
Q4, R4, A5, P5, Q5, P6, Q6, P7, Q7, R7, B9,
B10, B11, R11, P12, A14, B14, C14, G14, K14,
P14, Q14, R14, B15, Q15, B16, Q16
Analog ground
VEE, VEETH
H1, J1, L1, H2, J2, L2, M2, C3, H3, L3, M3, P3,
Q3, R3, A4, B4, C4, B5, C5, A8, B8, C8, C9, P9,
Q9, C10, Q10, R10
-5V analog supply (connected to same power supply
plane)
VPLUSD
P10, C11, P11, Q11, A12, B12, C12, Q12, R12,
D14, E14, F14, L14, M14, N14
Digital positive supply
DVEE
A13, B13, C13, P13, Q13, R13, H14, J14
-5V digital supply
Analog Inputs
VIN
R5
In-phase (+) analog input signal of the differential
Sample & Hold preamplifier
VINB
R6
Inverted phase (-) analog input signal of the differential
Sample & Hold preamplifier
Clock Inputs
CLK
E1
In-phase (+) clock input
CLKB
F1
Inverted phase (-) clock input
Digital Outputs
D0, D1, D2, D3, D4,
D5, D6, D7, D8, D9
D16, E16, F16, G16, J16, K16, L16, M16, N16,
P16
In-phase (+) digital outputs
D0 is the LSB, D7 is the MSB
D0B, D1B, D2B, D3B,
D4B, D5B, D6B, D7B,
D8B, D9B
D15, E15, F15, G15, J15, K15, L15, M15, N15,
P15
Inverted phase (-) digital outputs
OR
C16
In-phase (+) out-of-range output
ORB
C15
Inverted phase (-) out-of-range output
DR
H16
In-phase (+) data ready signal output
DRB
H15
Inverted phase (-) data ready signal output
Additional Functions
B/GB
A11
Binary or gray select output format control
- Binary output format if B/GB is floating or
connected to GND
- Gray output format if B/GB is connected to VEE
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