參數(shù)資料
型號(hào)： TS83102G0BVGL
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝： 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁數(shù)： 37/60頁
文件大?。?/td> 1510K
代理商： TS83102G0BVGL
42
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
13.6
Digital Outputs: Termination and Logic Compatibility
Each single-ended output of the TS83102G0B’s differential output buffers are internally 50
terminated,
and feature a 100
differential output impedance. The 50 resistors are connected to the VPLUSD dig-
ital power supply. The TS83102G0B output buffers are designed to drive 50
controlled impedance
lines properly terminated by a 50
resistor. A 10.5 mA bias current flowing alternately into one of the 50
resistors when switching, ensures a 0.25V
single-ended voltage drop across the resistor (0.5V differential).
Each single-ended output transmission line length must be kept identical (< 3 mm). Mismatches in the
differential line lengths may cause variations in the output differential common mode.
It is recommended to bypass the midpoint of the differential 100
termination with a 47 pF capacitor, so
as to avoid common mode perturbations in case of a slight mismatch in the differential output line
lengths.
See the recommended termination scenarios in Figures 46. and 47. below.
Note:
Since the output buffers feature a 100
differential output impedance, it is possible to directly drive high
the input impedance storing registers without terminating the 50
transmission lines. Timewise, this
means that the incident wave reflects at the 50
transmission line output and travels back to the 50 data
output buffer. Since the buffer output impedance is 50
, no
back reflection occurs and the output swing is doubled.
13.6.0.1
VPLUSD Digital Power Supply Settings
For differential ECL digital output levels: V
PLUSD should be supplied with -0.8V (or connected to
ground via a 5
resistor to ensure the -0.8 voltage drop).
For the LVDS digital output logic compatibility: V
PLUSD should be tied to 1.45V
(±75 mV).
If used with the TS81102G0 DMUX, V
PLUSD can be set to ground.
13.6.1
ECL Differential Output Termination Configurations
Figure 13-7. 50
Terminated Differential Outputs (Recommended)
10.5 mA
Zc = 50
OUT
VPLUSD = -0.8V
Zc = 50
50
50
OUTB
50
50
VOL typ = -1.17V
VOH typ = -0.94V
Differential Output Swing:
±0.23V = 0.46 Vpp
Common Mode Level = -1.05V
47 pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TS831-3IDT 功能描述:監(jiān)控電路 2.71V Micropower AL RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
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