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參數(shù)資料
| 型號(hào)： | TS88915T |
| 英文描述： | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| 中文描述： | TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時(shí)鐘驅(qū)動(dòng)器。 3國70和100兆赫的版本 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 333K |
| 代理商： | TS88915T |
1
Features
Vcc = 5V ± 5%
Military Temperature Range
Fully Compatible with the TS68040
Five Low Skew Outputs
– Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End
Frequency Locked to the SYNC Input
Three Additional Outputs are Available:
– The 2X_Q Output Runs Twice the System “Q” Frequency
– The Q/2 Output Runs At 1/2 the System “Q” Frequency
– The Q5 Output is Inverted (180
°
Phase Shift)
Two Selectable Clock Inputs
– Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes
– Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
– All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes
Input Frequency Range From 5 MHz to 2X_Q FMAX
Three Input/Output Ratios
– Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available
Low Part-to-part Skew
– The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is
Less than 550 ps (Derived From the tPD Specification, which Defines the
Part-to-part Skew)
CMOS and TTL Compatible
– All Outputs Can Drive Either CMOS or TTL Inputs
– All Inputs are TTL-level Compatible
LOCK Indicator (LOCK) Indicates a Phase-locked State
Description
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its
low skew outputs’ frequency and phase onto an input reference clock. It is designed to
provide clock distribution for high performance microprocessors such as TS68040,
TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM’s, MMU’s.
Screening/Quality
This Product is Manufactured:
Based Upon the Generic Flow of MIL-STD-883
or According to Atmel-Grenoble Standard
R suffix
PGA 29
Ceramic Pin Grid Array
W suffix
LDCC 28
Leaded Ceramic Chip Carrier
Low Skew
CMOS PLL
Clock Driver
Tri-State 70 and
100 MHz
Versions
TS88915T
Rev. 2122A–HIREL–06/02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS88915TMR70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 29PGA RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMW70 | 功能描述:IC CLK DVR 8OUT PLL 70MHZ 28LCCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| TS88915TMWB/T55 | 制造商:e2v technologies 功能描述: |
| TS88915TMWB/T70 | 制造商:e2v technologies 功能描述:PLL Clock Driver Single 35MHz to 70MHz 28-Pin LDCC |
| TS88915TVW100 | 功能描述:IC CLK DVR 8OUT PLL 28LCCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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