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參數(shù)資料
| 型號： | TS88915T |
| 英文描述： | TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions |
| 中文描述： | TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時(shí)鐘驅(qū)動器。 3國70和100兆赫的版本 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 333K |
| 代理商： | TS88915T |
14
TS88915T
2122A–HIREL–06/02
Notes Concerning Loop
Filter and Board Layout
Issues
1.
Figure 10 shows a loop filter and analog isolation scheme which will be effective
in most applications. The following guidelines should be followed to ensure sta-
ble and jitter-free operation:
All loop filter and analog isolation components should be tied as close to the
package as possible. Stray current passing through the parasitics of long traces
can cause undesirable voltage transients at the RC1 pin.
The 47
resistors, the 10 μF low frequency bypass capacitor, and the 0.1 μF
high frequency bypass capacitor form a wide bandwidth filter that will minimize
the 88915T’s sensitivity to voltage transients from the system digital V
CC
supply
and ground planes. This filter will typically ensure that a 100 mV step deviation
on the digital V
CC
supply will cause no more than 100 ps phase deviation on the
88915T outputs. A 250 mV step deviation on V
CC
using the recommended filter
values should cause no more than a 250 ps phase deviation; if a 25 μF bypass
capacitor is used (instead of 1 μF) a 250 mV V
CC
step should cause no more
than a 100 ps phase deviation. If good bypass techniques are used on a board
design near components which may cause digital V
CC
and ground noise, the
above described V
CC
step deviations should not occur at the 88915T’s digital V
CC
supply. The purpose of the bypass filtering scheme shown in Figure 10 is to give
the 88915T additional protection from the power supply and ground plane tran-
sients that can occur in a high frequency, high speed digital system.
There are no special requirements set forth for the loop filter resistors (1 M
and
330
). The loop filter capacitor (0.1 μF) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
The 1 M
reference resistor injects current into the internal charge pump of the
PLL, causing a fixed offset between the outputs and the SYNC input. This also
prevents excessive jitter caused by inherent PLL dead-band. If the VCO (2X_Q
output) is running above 40 MHz, the 1 M
resistor provides the correct amount
of current injection into the charge pump (2-3 μA). For the 70 and 100 MHz ver-
sions, if the VCO is running below 40 MHz, a 1.5 M
resistor should be used
(instead of 1 M
).
In addition to the bypass capacitors used in the analog filter of Figure 10, there
should be a 0.1 μF bypass capacitor between each of the other (digital) four V
CC
pins and the board ground plane. This will reduce output switching noise caused
by the 88915T outputs, in addition to reducing potential for noise in the ‘a(chǎn)nalog’
section of the chip. These bypass capacitors should also be tied as close to the
package as possible.
2.
3.
4.
5.
6.
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