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參數(shù)資料
| 型號： | TSB14C01MHV |
| 英文描述： | IC APEX 20KE FPGA 160K 484-FBGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 224K |
| 代理商： | TSB14C01MHV |
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6
–
14
6.5.2
Bus Reset
Once a PHY control request of Bus_Reset is communicated from the node controller to the PHY the PHY
communicates a Bus_Reset onto the bus.
NOTE:
Since a PHY transmitting a Bus_Reset must also react accordingly once the Bus_Reset
event is detected, its state machines do have the opportunity to advance beyond those of other
nodes. This ensures that all nodes are in a somewhat similar state after such a Bus_Reset
event.
Once a PHY detects that a Bus_Reset event has occurred on the bus, it communicates a bus reset status to the LLC.
The node controller initializes a bus reset by writing to the PHY control register with the IBR bit or IRBR bit set to 1.
The PHY hardware resets the IBR and IRBR bit to zero on detection of its own bus reset.
6.6
Live Insertion
It is up to the user to design the node or module to safely receive power from the particular backplane they are using
during a live insertion. But in principle, live insertion is supported and does not cause a bus reset event to occur.
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| TSB21LV03MHV | IC APEX 20KE FPGA 200K 484-FBGA |
| TSB21LV03CHV | IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER |
| TSB2203X6MMX30M | IC APEX 20KE FPGA 200K 240-PQFP |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14C01PM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TSB150002DS | 制造商:TE Connectivity 功能描述: |
| TSB150004DS | 制造商:TE Connectivity 功能描述:Conn Europa Terminal Blocks 8 POS 13.5mm Screw ST Cable Mount 40A/Contact |
| TSB150005 | 功能描述:柵欄接線端子 5P TERM BLOCK 13.5MM 300V 40A RoHS:否 制造商:TE Connectivity / AMP 產(chǎn)品:Barrier Terminal Blocks 系列: 類型:Dual Barrier, Flat Block without Mounting Ears 節(jié)距:9.53 mm 位置/觸點數(shù)量:2 線規(guī)量程:22-12 電流額定值:20 A 電壓額定值:300 V 安裝風格:Through Hole 安裝角:Vertical 端接類型:Screw 觸點電鍍:Tin |
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