參數(shù)資料
型號(hào)： TSC2101IRGZRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC48
封裝： GREEN, PLASTIC, VQFN-48
文件頁(yè)數(shù)： 46/95頁(yè)
文件大小： 1217K
代理商： TSC2101IRGZRG4
TSC2101
SLAS392D JUNE 2003 REVISED MAY 2005
www.ti.com
50
BIT
FUNCTION
READ/
WRITE
RESET
VALUE
NAME
D10
XSTAT
0
R
X Data Register Status
0 => No new data is available in Xdata register
1 => New data for Xcoordinate is available in register
Note: This bit gets cleared only after the converted data of X coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D9
YSTAT
0
R
Y Data Register Status
0 => No new data is available in Ydata register
1 => New data for Ycoordinate is available in register
Note: This bit gets cleared only after the converted data of Y coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D8
Z1STAT
0
R
Z1 Data Register Status
0 => No new data is available in Z1data register
1 => New data is available in Z1data register
Note: This bit gets cleared only after the converted data of Z1 coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D7
Z2STAT
0
R
Z2 Data Register Status
0 => No new data is available in Z2data register
1 => New data is available in Z2data register
Note: This bit gets cleared only after the converted data of Z2 coordinate has been completely read
out of the register. This bit is not valid in case of buffer mode.
D6
BSTAT
0
R
BAT Data Register Status
0 => No new data is available in BAT data register
1 => New data is available in BAT data register
Note: This bit gets cleared only after the converted data of BAT has been completely read out of the
register. This bit is not valid in case of buffer mode.
D5
0
R
Reserved
D4
AX1STAT
0
R
AUX1 Data Register Status
0 => No new data is available in AUX1data register
1 => New data is available in AUX1data register
Note: This bit gets cleared only after the converted data of AUX1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D3
AX2STAT
0
R
AUX2 Data Register Status
0 => No new data is available in AUX2data register
1 => New data is available in AUX2data register
Note: This bit gets cleared only after the converted data of AUX2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D2
T1STAT
0
R
TEMP1 Data Register Status
0 => No new data is available in TEMP1data register
1 => New data is available in TEMP1data register
Note: This bit gets cleared only after the converted data of TEMP1 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D1
T2STAT
0
R
TEMP2 Data Register Status
0 => No new data is available in TEMP2data register
1 => New data is available in TEMP2data register
Note: This bit gets cleared only after the converted data of TEMP2 has been completely read out of
the register. This bit is not valid in case of buffer mode.
D0
0
R
Reserved
相關(guān)PDF資料
PDF描述
TSC2101IRGZG4 SPECIALTY CONSUMER CIRCUIT, PQCC48
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