參數(shù)資料
型號(hào)： TSPC106AVGS66CG
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 28/40頁(yè)
文件大小： 569K
代理商： TSPC106AVGS66CG
28
TSPC106
2102B
–
HIREL
–
02/02
Output AC Specifications
Table 18 provides the output AC timing specifications as shown in Figure 10.
Notes:
1. Processor and memory interface signals are specified from the rising edge of the 60x bus clock.
2. Output specifications are measured from 1.4V on the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the signal in
question. Both input and output timings are measured at the pin.
3. The maximum timing specification assumes C
L
= 50 pF.
4. The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master driving them.
5. When the TSPC106 is configured for asynchronous L2 cache SRAMs, the DWE[0:2] signals have a maximum SYSCLK to
output valid time of (0.5 x t
PROC
) + 8.0 ns (where t
PROC
is the 60x bus clock cycle time).
6. PCI 3.3V signaling environment signals are measured from 1.65V (V
DD
÷
2) on the rising edge of SYSCLK to V
OH
= 3.0V or
V
OL
= 0.3V.
7. The minimum timing specification assumes C
L
= 50 pF.
8. t
SYSCLK
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as t
SYSCLK
, the num-
bers given in the table must be multiplied by the period of SYSCLK to compute the actual duration in nanoseconds of the
parameter in question.
9. These values are guaranteed by design and are not tested.
10. PCI devices which require more than the PCI-specified hold time of T
H
= 0 ns or systems where clock skew approaches the
PCI-specified allowance of 2 ns may not work with the TSPC106. For workarounds, see Motorola application note
“
Design-
ing PCI 2.1-compliant MPC106 Systems
”
(order number AN1727/D).
Table 18.
Output AC Timing Specifications (V
DD
= 3.3V ± 5% dc, GND = 0V dc, C
L
= 50 pF, -55
°
C
≤
T
C
≤
125
°
C)
Ref
Characteristic
66 MHz
83.3 MHz
Unit
Min
Max
Min
Max
12
SYSCLK to output driven (output enable
time)
(9)
2.0
2.0
ns
13a
SYSCLK to output valid (for TS and
ARTRY)
(1, 2, 3, 4)
7.0
6.0
ns
13b
SYSCLK to output valid (for all non-PCI
signals except TS, ARTRY, RAS[0:7] and
CAS[0:7]) and DWE[0:2]
(1, 2, 3, 5)
7.0
6.0
ns
14a
SYSCLK to output valid (for RAS[0:7] and
CAS[0:7])
(1, 2, 3)
7.0
6.0
ns
14b
SYSCLK to output valid
(for PCI signals)
(3, 6)
11.0
11.0
ns
15a
SYSCLK to output invalid for all non-PCI
signals (output hold)
(7, 10)
1.0
1.0
ns
15b
SYSCLK to output valid for PCI signals
(output hold)
(7)
1.0
1.0
ns
18
SYSCLK to ARTRY high impedance
before precharge (output hold)
(9)
8.0
8.0
ns
19
SYSCLK to ARTRY precharge enable
(8, 9)
(0.4 x t
SYSCLK
)
+ 2.0
(0.4 xt
SYSCLK
)
+ 2.0
ns
21
SYSCLK to ARTRY high impedance after
precharge
(8, 9)
(1.5x t
SYSCLK
)
+ 8.0
(1.5 xt
SYSCLK
)
+ 8.0
ns
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