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參數(shù)資料
| 型號： | TVP5031CPFP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color Decoder Circuit |
| 中文描述： | 彩色解碼器電路 |
| 文件頁數(shù)： | 26/85頁 |
| 文件大?。?/td> | 378K |
| 代理商： | TVP5031CPFP |
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2–10
2.2.4
Chrominance Processing
A quadrature demodulator extracts U and V components from the composite signal. The U/V signals then pass
through the gain control stage for chroma saturation adjustment. A comb filter is applied to both U and V to eliminate
cross-chrominance noise. Hue control is achieved with phase shift of the digitally controlled oscillator. An automatic
color killer (ACK) circuit is also included in this block. The ACK will suppress the chroma processing when the color
burst of the video signal is weak or not present.
2.2.5
Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. Figure 2–18 shows a simplified clock circuit
diagram. The digital control oscillator (DCO) generates the reference signal for the horizontal PLL. A 14.318 MHz
clock is required to drive the DCO. This may be input to the TVP5031 at TTL level on the XTAL1 terminal, or a crystal
of 14.318 MHz fundamental resonant frequency may be connected across terminals XTAL1 and XTAL2. Figure 2–19
shows the reference clock configurations. For the example crystal circuit shown in Figure 2–19 (a parallel-resonant
crystal with 14.31818 MHz fundamental frequency), the external capacitors should have the following relationship:
C
L1
= C
L2
= 2C
L
– C
stray
Where C
stray
is the terminal capacitance with respect to ground.
Lowpass Filter
Sync Detector
Digitized
Video
XTAL1
Phase
Detector
Loop
Filter
Digital
Control
Oscillator
XTAL2
Crystal
Clock
Generator
Clock
Generation
Circuit
Line-Locked
Clock
PLL
SCLK
PCLK
Figure 2–18. Clock Circuit Diagram
TVP5031
35
XTAL1
14.31818 MHz
Crystal
36
XTAL2
TVP5031
35
XTAL1
36
XTAL2
CL1
CL2
14.31818 MHz
TTL Clock
Figure 2–19. Example Reference Clock Configurations
The TVP5031 generates three signals PCLK, SCLK, and PREF used for clocking data. PCLK, the pixel clock, can
be used for clocking data in the 20-bit and 16-bit 4:2:2 output formats. SCLK is twice the PCLK frequency and may
be used for clocking data in the 10-bit and 8-bit 4:2:2 as well as in ITU-R BT.656 formats. PREF is used as a clock
qualifier with SCLK to clock data in the 20-bit and 16-bit 4:2:2 formats.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5031TQFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
| TVP5040CPFP | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040CPFPG4 | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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