參數(shù)資料
型號： TVP5031CPFP
廠商： Texas Instruments, Inc.
英文描述： Color Decoder Circuit
中文描述： 彩色解碼器電路
文件頁數(shù)： 44/85頁
文件大小： 378K
代理商： TVP5031CPFP
2–28
VBI FIFO
The VBI FIFO containing sliced VBI data can be read directly by the PHI host.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read VBI FIFO
1
0
Data from FIFO
Status/Interrupt Register
The status/interrupt register provides the host with information regarding the source of an interrupt. After an interrupt
condition is set it can be reset by writing a 1 to the appropriate bit in the status/interrupt register. Section 2.14 contains
a description of the PHI status/interrupt register.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Access status/interrupt register
1
1
Data from status/interrupt register
2.6.6
Parallel Host Interface Microcode Write Operation
Data written to indirect register 7E will be written to the TVP5031 program RAM. During the write cycle the
microprocessor will reset and point to location zero in the program and will remain reset. Upon completion of the write
operation, a microprocessor clear-reset operation is required. This is performed by writing into the 7F register to clear
reset and resume microprocessor function. (There is no specific data requirement to be written into the 7F register,
any data will resume microprocessor function.)
To avoid violating PHI cycle time requirements during a microcode write operation the host can poll the cycle complete
bit in the PHI status register after writing each byte data to the PHI data register. Alternatively, the cycle complete
enable bit in the interrupt enable register (indirect address C1) can be set to generate an interrupt for the host when
a write has been completed.
A1
0
A0
0
D7
0
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
0
Write microcode register address
A1
0
A0
1
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode register data
First byte of microcode data
(Wait for cycle complete status or interrupt.)
Write microcode register data
0
1
Second byte of microcode data
(Wait for cycle complete status or interrupt.)
Write microcode register data
0
1
Last byte of microcode data
(Wait for cycle complete status or interrupt.)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset dummy data
0
1
Dummy data
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