CHAPTER 5 MEMORY MANAGEMENT SYSTEM
118
Figure 5-1. Virtual-to-Physical Address Translation
Virtual address
The offset is then added to the PFN
passing through the TLB.
If there is a match, the page frame
number (PFN) representing the high-
order bits of the physical address is
output from the TLB.
The virtual page number (VPN) in the
virtual address (VA) is compared with
the VPN in the TLB.
TLB
entry
Physical address
3
2
TLB
1
ASID
Offset
VPN
Offset
PFN
PFN
G
ASID
VPN
5.2.1 Virtual-to-Physical Address Translation
Converting a virtual address to a physical address begins by comparing the virtual address from the processor
with the virtual addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the
same as the VPN field of the entry, and either:
—
the Global (G) bit of the TLB entry is set to 1, or
—
the ASID field of the virtual address is the same as the ASID field of the TLB entry.
This match is referred to as a TLB hit. If there is no match, a TLB Mismatch exception is taken by the processor
and software is allowed to refill the TLB from a page table of virtual/physical addresses in memory.
If there is a virtual address match in the TLB, the physical address is output from the TLB and concatenated with
the offset, which represents an address within the page frame space. The offset does not pass through the TLB.
Instead, the low-order bits of the virtual address are output without being translated. See descriptions about the
virtual address space for details. For details about the physical address, see
5.4.9 Virtual-to-Physical Address
Translation
.
The next two sections describe the 32-bit and 64-bit mode address translations.