CHAPTER 15 PMU (POWER MANAGEMENT UNIT)
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Table 15-3. Power Mode
Mode
Internal peripheral unit
CPU core
RTC
ICU
DCU
others
Fullspeed
On
On
On
Selectable
Note
On
Standby
On
On
On
Selectable
Note
Off
Suspend
On
On
Off
Off
Off
Hibernate
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Note
See Chapter 13 for details.
(1) Fullspeed Mode
In Fullspeed mode, all internal clocks and the bus clock operate. In this mode, all the functions of the V
R
4102
can be executed.
(2) Standby Mode
In Standby mode, all internal clocks, other than those provided to the internal peripheral units and the internal
timer/interrupt unit of the CPU core, are fixed to high level.
To switch to Standby mode from Fullspeed mode, first execute the STANDBY instruction. The V
R
4102 waits until
the SysAD bus (internal) enters idle status after the completion of the WB stage of the STANDBY instruction. Then,
the internal clock is shut down, and the pipeline stops. PLL, timer/interrupt clock, internal bus clocks (TClock,
MasterOut), and RTC continue to operate.
In Standby mode, the processor returns to Fullspeed mode when an interrupt occurs. At this time, the contents of
bits indicating the states of pins in the peripheral unit’s registers are undefined. The contents of other fields are
retained.
(3) Suspend Mode
In Suspend mode, all internal clocks (including TClock) other than those supplied to the RTC/ICU/PMU internal
peripheral units and the internal timer/interrupt unit of the CPU core are fixed to high level.
To switch to Suspend mode from Fullspeed mode, first execute the SUSPEND instruction. The V
R
4102 waits
until the SysAD bus (internal) enters idle status after the completion of the WB stage of the SUSPEND instruction,
DRAM has entered self-refresh mode, and the MPOWER pin has been made inactive. Then, the internal clocks
(including TClock) are shut down, and the pipeline stops. PLL, timer interrupt clock, MasterOut, and RTC continue
to operate.
If the SUSPEND instruction is executed during DMA transfer, the DRAM transfer is suspended, and operation is
undefined.
In Suspend mode, the processor returns to Fullspeed mode when an interrupt request from the peripheral units or
any resets occur. At this time, the contents of bits indicating the states of pins in the peripheral unit’s registers are
undefined. The contents of other fields are retained.